Subject: Re: Building for both ARM V4 and ARM V5 systems
To: Richard Earnshaw <Richard.Earnshaw@buzzard.freeserve.co.uk>
From: Richard Earnshaw <Richard.Earnshaw@buzzard.freeserve.co.uk>
Date: 08/06/2006 23:07:52
On Sun, 06 Aug 2006 21:47:40 BST, David Laight <firstname.lastname@example.org> wrote:
> On Sat, Aug 05, 2006 at 02:04:42AM +0100, Richard Earnshaw wrote:
> > >
> > > volatile ushort ptr = /* WHATEVER THE DEVICE ADDRESS is MAPPED to */
> > > ushort value;
> > >
> > > *ptr = value; /* If you want to store to the device */
> > > value = *ptr; /* If you want to read from it. */
> > >
> > > The problem is that the compiler generates two byte operations for
> > > such a reference, rather than one half word operation, for V4.
> > Nonsense. ARMv4 has half-word operations and if you use -march=armv4 the
> > compiler will use them.
> But, IIRC, that range of offsets is less for the half-word operations,
> and gcc is likely to use 32bit operations to read 16bit values (masking
> the high bits). Even using misaligned transfers for 4n+2 addresses.
> (or do we disable that in netbsd's versions of gcc?)
Sorry, you remember incorrectly; at least for V4.
NetBSD/arm hasn't supported unaligned accesses to half-word memory since
the ARM port switched to ELF. GCC stopped generating unaligned word
accesses of any kind on ARM in gcc-3.4. This is to ensure that code built
for legacy cpus will continue to work correctly on v6 devices which
support traditional unaligned memory access semantics.