Subject: Re: Support for ARM9E
To: Richard Earnshaw <Richard.Earnshaw@buzzard.freeserve.co.uk>
From: Scott <firstname.lastname@example.org>
Date: 07/27/2006 15:53:57
Richard Earnshaw wrote:
> Hmm, is your 'firmware' passing control to NetBSD with the MMU enabled?
> For most ports that's considered to be a no-no, and in those cases the
> first thing they do is turn the MMU off. It makes the bootstrap code
> slower, but it then does work reliably.
In my _start.S, I ensure that the MMU is off and then I go ahead and get
things going similar to the way that it is done in lubbock_start.S. After
doing that, I go virtual and jump to start. Things work fine unless the
Buffering for my SDRAM translation table entries that I set up in my _start.S
don't match how they get set up by pmap. I suspect that changing the TTB
while there are some "live" dcache entries is not a "recommended" procedure
and if the buffering of the "live" entry doesn't match what is in the new
translation table, chaos ensues.
>>I checked the ARM1026EJ-S TRM and it supports these same operations. The
>>question is, does anyone know why NetBSD loops over all the sets/ways instead
>>of using the nifty operations?
> That would be because the ARM1020E doesn't have those cache operations :-(
> I thought I'd already added some support for the operations you mention,
> but I can't find it in my tree here. Maybe it was at work.
Ah, so to use them, CPU_ARM10 would have to become smarter, or perhaps,
CPU_ARM10E would have to be added.