Subject: Re: ARM cache and MMU
To: None <email@example.com>
From: Toru Nishimura <firstname.lastname@example.org>
Date: 01/18/2005 20:36:53
> Note: With respect to the wider context of this discussion, ARM
> Architecture 6 (ARMv6) permits cache implementations that are Physically
> Indexed Physically Tagged or Virtually Indexed Physically Tagged.
Thanks, Richard. Readers should also consult with pp.335-336 of Prof. Furber
book about ARM920 improvements over ARM8.
Toru Nishimura/ALKYL Technology, NetBSD protects your investment.