Subject: Re: ARM cache and MMU
To: Toru Nishimura <email@example.com>
From: Richard Earnshaw <firstname.lastname@example.org>
Date: 01/18/2005 11:14:52
On Tue, 2005-01-18 at 07:58, Toru Nishimura wrote:
> In restrospective, ARM shows its origin, born to replace 6502 processor. MMU
> and cache have been emphasized less. The spectacular failure of ARM8
> indicates the designers are unaware of how to make CPU process-model OS
> friendly with minimal transistor counts.
ARM8 was only a 'failure' in the relative light of the phenomenal
success of the ARM7TDMI.
Architecturally, and from an OS perspective, the ARM8 and StrongARM were
very similar, so to claim that the ARM8 was a failure because of its
design would imply that StrongARM should equally have been a failure
from that stand point. The success of StrongARM clearly demonstrates
that this was not the case. In fact, the unified cache architecture of
the ARM8 and the availability of a write-through cache mode made OS
design easier than on the StrongARM.
The main reason, as I see it, that the ARM8 didn't become as popular as
the ARM7TDMI, or the ARM9 that followed was that they had Thumb, whereas
the ARM8 didn't. In many respects, ARM9 was the evolution of ARM8 with
Thumb added in.
Note: With respect to the wider context of this discussion, ARM
Architecture 6 (ARMv6) permits cache implementations that are Physically
Indexed Physically Tagged or Virtually Indexed Physically Tagged.
[All opinions expressed are my own].