Subject: Re: ARM cache
To: None <>
From: Toru Nishimura <>
List: port-arm
Date: 01/17/2005 12:16:09
Some more to say for cache design.

Alchemy Au1 cache is designed smart;
- 16KB I and D, virtual address indexed and physical address tagged,
best fit for process model OS,
- 4 way associativity. Note that it means Au1 cache behaves as a
physical address indexed and physical address cache.  This
arrangement saves a lot i*norant programmers since the world is
dominated by PA cache processors.
- write back policy, but it does bus snoop.  This mean there is *no* need
of busdma_sync() for device driver to work correct.

Some MIPS processors  have VA tagged instruction cache.  ASID may
or may not be a part of cache indexing.  Since instruction cache is not
supposed written, the design decision seems reasonable.
Toru Nishimura/ALKYL Technology, a NetBSD company