Subject: ARM cache
To: None <email@example.com>
From: Toru Nishimura <firstname.lastname@example.org>
Date: 01/17/2005 12:03:42
> IIRC, context switches are very expensive on arm due to the
> virtually-indexed L1 cache flushing. Is the pagedaemon kernel thread the
> one needing to run this often and therefore competing with ttcp?
pagedaemon is one of "all-kernel-space" runtime context and makes no
address space switching. It's true that virtual-indexed nature of ARM
processor is very ill-fit with Unix style process model OS anyway.
> * bypass most dmamap_sync() and use DMA_COHERENT mappings
I'm afraid ARM cache is not designed for bus snooping. Given relatively
high associativity with small capacity in size the possiblity of cache
inconsistency is statistically small for real load, however it would happen.
Toru Nishimura/ALKYL Technology, Linux does not help a company; Apple.