> I noticed that on some of the Intel XScale processors only Big endian =
> mode is allowed, so I figure the dual compatible endian mode processors =
> has to do some conversion internally in one of the modes not native to =
> the execution unit.
>
> Filip

As long as a processor is designed in truly straight RISC discipline, there
is no chance to constraint endianess inside processor core.  The core itself can
be designed endian-neutral, i.e., no hardwired endianess and "incore
conversion" back-and-forth.  Mixed endianness does matter at data path
outside of core, at SoC internal-connect or at bus/peripheral-connect.

Sometimes it's hard to keep entire hardware design endian-neutral, and
more-or-less endian conversion efforts must be done either by hardware
circuit design or device driver software.  Making XScale big-endian only
can not wipe out endian conversion in practice and the decision was made
by other reason(s) than "performance penalty."

Toru Nishimura/ALKYL Technology