Subject: ARM9 cache routines updated
To: None <email@example.com>
From: Richard Earnshaw <firstname.lastname@example.org>
Date: 01/26/2004 16:07:58
I've just updated the ARM9 cache routines so that the processor uses its
Dcache in write-back mode; this should improve performance somewhat.
While I was there I also found a bug in the way the ARM9 code was
configuring the system control register (cp15,r1), which was forcing the
core back into FastBus mode (where the core effectively is running off the
memory bus clock :-( ). This should improve performance significantly,
especially if the firmware has set the system clocks up correctly :-)
If anyone has access to the various Samsung ARM920-based boards I'd be
interested to hear how this affects performance.