Subject: Re: Xscale optimisations
To: David Laight <>
From: Richard Earnshaw <>
List: port-arm
Date: 10/14/2003 13:54:15
> Does anyone know if the SA1100 ever generates a memory burst for a stmia 
> that write that misses the cache?

StrongARM load/store multiple instructions are expanded in the pipeline 
into a sequence of equivalent load/store word operations (which is why 
they take a long time to *not* execute if the condition fails).  A 
sequence of stores that miss the cache will go direct to the write buffer. 
 Provided that write-coalescing is enabled, this will be used to form a 
burst on the memory bus.