"Jason R Thorpe" <thorpej@wasabisystems.com> said;

> I wonder if any ARMv6 CPUs will come with a PU rather than an MMU...

Variable page length TLB entries, hardwared  (BATC), with simple helps of
ITLBmiss and DTLBmiss handlers, combined with WATCH register (PA or
VA) for no-trepassing zone.  These fulfill what industry's RTOS demands,
with big margin.

Toru Nishimura/ALKYL Technology