Subject: Re: plan to merge cats and netwinder isa_machdep.c
To: None <>
From: Chris Gilbert <>
List: port-arm
Date: 10/09/2002 19:21:41
Izumi Tsutsui said:
> In article <>
> wrote:
>> I'm thinking of merging the cats and netwinder isa_machdep.c files
>> into one, and placing it under arm/footbridge/isa/
> A bit off topic, but does ISA DMA work on these ports?
> Last time I tried AHA-1542 and PCnet-ISA on cats,
> both of them didn't work at all.

No idea, I've not tried ISA cards in my cats, I plan to at some point
soon, but first I suspect that the mess that is isa with footbridge needs
tidying up.  It doesn't surprise me if they didn't work, currently isa
interrupts happen at IPL_BIO on the footbridge, so if we go to splbio or
higher no isa interrupts will get through, this means that any other
footbridge interrupts can block the isa ones very easily.

What I believe should happen is that the isa bus is mapped in on a higher
IPL (IPL_HIGH possibly, better to map it at the level of the highest thing
it runs at) and that the spl* calls actually also change the isa
interrupts being blocked, and that the isa interrupt dispatch checks the
spl etc.

But I need to run this by people with more knowledge/experience of these
things, am I just mad, and it might just work, or is it just madness 8)

Certainly my new code for footbridge should work well (as I keep the
current ipl level as a number, not a mask, so it's use in isa would work)

> Current _isa_bus_dmamap_load() in footbridge/isa/isadma_machdep.c
> returns physical address for ds_addr, but is it really OK for 24bit ISA
> bus? And does cats really require bounce-buffer for isadma?

No idea, I believe it'll need the standard pc method of bounce buffers, as
it's a standard PC ali southbridge.

> Furthermore, _isa_bus_dmamap_sync() does not handle cache coherency at
> all, but it should do like arm/arm32/bus_dma.c.

pah, who cares about cache coherency, it's what makes life interesting 8)

Certainly the isa interrupt code needs lots of work, I've taken the first
step by tidying up the footbridge irq handling, but we need to allow for
isa interrupts to happen at the correct IPL levels.