Subject: Re: Using different cache modes for r/o vs r/w pages
To: John Clark <>
From: Jason R Thorpe <>
List: port-arm
Date: 01/31/2002 19:02:54
On Wed, Jan 30, 2002 at 11:43:01PM -0800, John Clark wrote:

 > If this refers to the X bits in the XScale PTE discription, this is a 
 > pretty important
 > cache mode for Xscale. (Enable Write Allocate as I recall.)

Yah, the cool extended cache mode on Xscale is called "write-allocate".
In this mode, a store that misses the D$ cache also causes a line-fill.
In normal write-back mode, a store that misses the D$ doesn't stay in
the cache, it just goes on to the write buffer.

Note I'm not actually using the X bit yet.  This is one of the things
my infrastructure changes will allow me to do (in addition to working
around some errata that affects i80200 cores all the way through C-step).

The "prototype PTE" infrastructure is important; use of the X bit requires
that the L2 PTE have a different type (0x3), and the AP bits are different
(as in, there is only one set of AP bits, since the extended small page type
does not support sub-pages).

Section mappings and large pages can also use the X bit.

        -- Jason R. Thorpe <>