Subject: Re: Using different cache modes for r/o vs r/w pages
To: None <>
From: John Clark <>
List: port-arm
Date: 01/30/2002 23:43:01
Am Dienstag den, 29. Januar 2002, um 20:53, schrieb Jason R Thorpe:

> Hi folks...
> The patch essentially does:
> 	* Replace PT_CACHEABLE with a pte_cache_mode[] array, indexed
> 	  by protection code (e.g. VM_PROT_READ, VM_PROT_READ|VM_PROT_WRITE,
> 	  etc.)  Replace all uses of PT_CACHEABLE with an access of the
> 	  array.

If this refers to the X bits in the XScale PTE discription, this is a 
pretty important
cache mode for Xscale. (Enable Write Allocate as I recall.)

Unfortunately, it has been a while since I looked at this; I don't have 
my manual
handy; I started looking at the pmap stuff pretty late tonight, so...

What files are the PTE bits being set in relative to 'sys/arch/...'... 
I've found arm/arm32/pmap.h

But it seems that in the interest of re-usability, macros, tardiness of 
night, I can't see where the PTE's are fiddled with to check on these