Subject: Re: Using different cache modes for r/o vs r/w pages
To: None <Richard.Earnshaw@arm.com>
From: Jason R Thorpe <firstname.lastname@example.org>
Date: 01/30/2002 08:07:27
On Wed, Jan 30, 2002 at 12:08:05PM +0000, Richard Earnshaw wrote:
> Given your need to recalculate the cacheable bits here, the above approach
> may no-longer be the best. It might be the case that we should now make
> the cacheability of a page based on the current PTE writable attribute
> rather than the UVM attributes for the page.
Hm. Then perhaps the best approach is to have a "pte_prot_proto" array,
one for cacheable, one for non-cacheable, that has the AP_* bits as well
as the PT_B and PT_C bits.
Actually, now that I think about it, this does make more sense in the
long run, since the use of some extended caching modes available on
XScale overlap with some of the AP_* bits, I believe... hm, I'll have
to look at the manual to double-check that (but after I get back from
the dentist .. eek).
-- Jason R. Thorpe <email@example.com>