Subject: Re: RFC: Change SWI number base?
To: David Laight <David.Laight@btinternet.com>
From: Richard Earnshaw <email@example.com>
Date: 01/09/2002 10:48:41
> No need, "align 0" has always meant "word aligned" for traditional
> > compatibility with old assemblers (pre gas).
> Is that 2-byte of 4-byte here?
.align 0 always give 4-byte alignment.
> The 'pc' value when the 'bx pc' is done MUST be a multiple of 4.
> Apparantly (inspite of what the ARM ARM may have said) some cpus
> don't ignore bit 1 of the pc when doing pc relative loads - so
> find all your constants rotated by 16 bits :-)
Eh? Can you cite examples?
> If (many) of the syscall hooks are in one file, making the final sequence:
> swi nnn
> bxcc lt
> b __go_cerror
> ldr r12,=__cerror
> bx r12
> saves a few bytes and makes each hook 16 bytes - so they fit niceley
> into cache lines.
But costs an extra non-predictable branch (very expensive on XScale). I'm
not suggesting that we should look at something like this, but the cost
has to be borne in mind.
> Now work out the optimal order for the hooks, then
> get the .balign 32 to work (it doesn't in the arm a.out build I've used).
a.out object files on ARM only maintain the sections to 4-byte alignment,
so will ignore attempts to force greater alignment. The linker simply
concatenates each similar section ensuring that they start on a 4-byte