Subject: Re: RFC: Change SWI number base?
To: None <email@example.com>
From: David Laight <David.Laight@btinternet.com>
Date: 01/09/2002 09:49:33
> > > .code 16
> > > .align 0
> > > SWI_nnn:
> > > bx pc /* Switch to arm code */
> > > nop
> > > .code 32
> > > swi nnn
> > > ldrcs ip, L__cerror
> > > bxcc lr /* Return if no error */
> > > bx ip
> > Yes - fairly neat. Need to get the alignment right though.
> > think that requires a .align 2 (or a .balign 4), and a sanity check!
> No need, "align 0" has always meant "word aligned" for traditional
> compatibility with old assemblers (pre gas).
Is that 2-byte of 4-byte here?
The 'pc' value when the 'bx pc' is done MUST be a multiple of 4.
Apparantly (inspite of what the ARM ARM may have said) some cpus
don't ignore bit 1 of the pc when doing pc relative loads - so
find all your constants rotated by 16 bits :-)
> > pull the 'bxcc lr' up an instruction...
> It's currently in the delay slot for the load instruction (though you
> might argue that failure is sufficiently rare that it isn't worth the
> extra cycle for the non failure case in order to save a cycle for the
> failure case).
I would go further - the load instruction probably missed the d-cache
so you really don't want to do it in the 'success' path.
> Note that if we knew __cerror was arm code we could simplify the final
> sequence to
> swi nnn
> bxcc lr
> b __cerror
If (many) of the syscall hooks are in one file, making the final sequence:
saves a few bytes and makes each hook 16 bytes - so they fit niceley
into cache lines. Now work out the optimal order for the hooks, then
get the .balign 32 to work (it doesn't in the arm a.out build I've used).