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Ben Harris <bjh21@netbsd.org> writes:

> On 27 May 2001, John Fremlin wrote:
> 
> > Introduced are three new functions
> >
> >         __SetCPSR /* Force the CPSR to a certain value */
> >         __set_stackptr /* set_stackptr without changing mode */
> >         __get_stackptr /* get_stackptr without changing mode */
> >
> > the first of which is helpful.
> 
> Why the underscores at the start? 

They are helper functions.

> For the first, we presumably don't have an existing SetCPSR, 

One exists already. The __SetCPSR is just a simpler primitive -
i.e. no worrying about bitmasks etc.

(IIRC hpc port defines SetCPSR as "extern" instead of using the
cpufunc.h header. Talk about a crufty codebase.)

> and for the others, wouldn't "set_current_stackptr" be a better name
> (assuming that's what it does)?

Ok.

> Is there any point in having functions that aren't helpful?

They are used as the actual lowlevel primitives.

> > Would this patch be accepted?
> 
> Probably.  I really need to overhaul cpufunc properly one day, but
> patches to make it nicer are always helpful.

Here is the patch. After it is merged and explicit extern decls are
fixed, the assembly files implementing the stackptr and CPSR routines
can be removed. Note that the psionw port is not yet able to usefully
test these routines, so they might be doing completely the wrong
thing, and because I renamed the __?et_stack_pointer functions the
patch might not even compile :-)


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Content-Type: text/x-patch
Content-Disposition: attachment;
  filename=netbsd-20010529-cpufunc-inline.patch

Index: cpufunc.h
===================================================================
RCS file: /pub/NetBSD-CVS/syssrc/sys/arch/arm/include/cpufunc.h,v
retrieving revision 1.2
diff -u -r1.2 cpufunc.h
--- cpufunc.h	2001/03/06 22:29:13	1.2
+++ cpufunc.h	2001/05/29 01:34:42
@@ -285,19 +285,83 @@
 
 /*
  * Functions to manipulate the CPSR
- * (in arm32/arm32/setcpsr.S)
  */
 
-u_int SetCPSR		__P((u_int bic, u_int eor));
-u_int GetCPSR		__P((void));
+static __inline u_int GetCPSR(void)
+{
+	u_int psr;
+	__asm __volatile("mrs %0, CPSR" : "=r" (psr));
+	return psr;
+}
 
+/* Force the CPSR to a certain value */
+static __inline void __SetCPSR(u_int psr)
+{
+	__asm __volatile("msr CPSR_all, %0" : /* no outputs */
+	    : "r" (psr)
+	    : "r8","r9","r10","r11","r12","r13","r14"
+	    /*clobber everything, as if we magically switched
+	     * out of FIQ mode */);
+}
+
+
+static __inline u_int SetCPSR(u_int mask, u_int eor)
+{
+	u_int psr = GetCPSR();
+	psr &= ~mask;
+	psr ^= eor;
+	__SetCPSR(psr);
+	return psr;
+}
+
 /*
  * Functions to manipulate cpu r13
- * (in arm32/arm32/setstack.S)
  */
+
+
+/* set_stackptr without changing mode */
+void
+static __inline set_current_stackptr(u_int address)
+{
+	__asm __volatile("mov r13, %0" : /* no outputs */
+	    : "r" (address)
+	    : "r13" );
+}
+
+void
+static __inline set_stackptr(u_int mode, u_int address)
+{
+	u_int32_t psr = GetCPSR();
+	
+	SetCPSR(PSR_MODE, mode&PSR_MODE);
+	set_current_stackptr(address);
+	
+	__SetCPSR(psr); 
+}
+
+/* get_stackptr without changing mode */
+u_int
+static __inline get_current_stackptr(void)
+{
+	u_int address;
+	__asm __volatile("mov %0, r13" 
+	    : "=r" (address));
+	return address;
+}
 
-void set_stackptr	__P((u_int mode, u_int address));
-u_int get_stackptr	__P((u_int mode));
+u_int
+static __inline get_stackptr(u_int mode)
+{
+	u_int32_t psr = GetCPSR();
+	u_int address;
+	
+	SetCPSR(PSR_MODE, mode&PSR_MODE);
+	address = get_current_stackptr();
+	
+	__SetCPSR(psr);
+	
+	return address;
+}
 
 /*
  * CPU functions from locore.S

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