After I've updated -current sources from 20011108 to 20011121,
my Express5800/230 (JC94) no longer boots with newer kernels.

The kernel got "TlbL exception" and droped into the ARC BIOS monitor:
---
Monitor. Version 5704
Press H for help, Q to quit.
TlbL exception occurred.
 at=00000000 v0=00010007 v1=80422698 a0=801ffe30 a1=801ffef4 a2=801ffc80
 at=00000000 t0=00000000 t1=00000010 t2=801ffd10 t3=80422698 t4=8047b71c
 t5=00000003 t6=00000003 t7=00000000 s0=801fff7c s1=00000100 s2=8047b800
 s3=0000000c s4=00000008 s5=8000b830 s6=00000000 s7=00000029 t8=801ffd00
 t9=0000000d k0=8004d640 k1=80000194 gp=8045ad50 sp=801ffc60 s8=801ffe30
 ra=800247ec psr=20000002 epc=8038ecf0 cause=30008008 errorepc=e11f0d0c
 badvaddr=00000000
>
---
0x8038ecf0 is address of cpu_Debugger(), and 0x80422698 is
the string address of panic("r4k picache line size %d" ..)
in arch/mips/mips/cache.c:mips_config_cache().
I guess cn_tab is disabled in this point so the kernel
drops into the monitor.

I think this panic is caused because the line size of L1 cache
on JC94 is 32:

>cpu0 at mainbus0: MIPS R4400 CPU (0x460) Rev. 6.0 with MIPS R4010 FPC Rev. 0.0
>cpu0: L1 cache: 16KB/32B instruction, 16KB/32B data, direct mapped
>cpu0: L2 cache: 1024KB/64B mixed, no snooping

so should we also have 32B/line L1 cache ops for r4k?
---
Izumi Tsutsui
tsutsui@ceres.dti.ne.jp