In article <87u1z72ghu.wl@alicia.a-r.org>
ur@a-r.org wrote:

> NEC firmware seems incomplete to configure PCI devices. but situation
> is not so bad. I think just fixing few configuration registers is enough.
> 
> I'll commit my patch later.

Unfortunately, 53c875 with siop driver no longer works
even with your patch.

Backing out pmap_kenter_pa() changes in mips/pmap.c rev 1.127
makes siop work again, so I think the problem is that newer
pmap_kenter_pa() implicitly maps pages with MIPS3_PG_CACHED.
(pmap_kenter_pa() is called from arc_sparse_bus_space_compose_handle()
 in arc/arc/bus_space_sparse.c, which is not used by TGA.)

The attached patch also fixes the problem, but how can we
determine whether the specified PA is cachable or not
in pmap_kenter_pa()? Or is pmap_kenter_pa() used only
for device memory (== unmanaged memory) on mips?
(I'm not a mips guy..)
---
Izumi Tsutsui
tsutsui@ceres.dti.ne.jp

Index: pmap.c
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/mips/mips/pmap.c,v
retrieving revision 1.131
diff -u -r1.131 pmap.c
--- pmap.c	2001/08/26 06:03:11	1.131
+++ pmap.c	2001/08/29 16:44:49
@@ -1324,15 +1324,14 @@
 #endif
 
 	npte = mips_paddr_to_tlbpfn(pa) | mips_pg_wired_bit();
-	if (prot & VM_PROT_WRITE) {
-		npte |= mips_pg_rwpage_bit();
-	} else {
-		npte |= mips_pg_ropage_bit();
-	}
 	if (CPUISMIPS3) {
-		npte |= MIPS3_PG_G;
+		npte |= (prot & VM_PROT_WRITE) ?
+		    MIPS3_PG_IOPAGE :
+		    ((MIPS3_PG_IOPAGE | MIPS3_PG_RO) & ~MIPS3_PG_D);
 	} else {
-		npte |= MIPS1_PG_V | MIPS1_PG_G;
+		npte |= (prot & VM_PROT_WRITE) ?
+		    MIPS1_PG_D | MIPS1_PG_N | MIPS1_PG_V | MIPS1_PG_G :
+		    MIPS1_PG_RO | MIPS1_PG_N | MIPS1_PG_V | MIPS1_PG_G;
 	}
 	pte = kvtopte(va);
 	KASSERT(!mips_pg_v(pte->pt_entry));