So here's a recap of where I'm at with the Magnum 4000SC...
The 4000SC, unlike the 4000PC, has only ONE actual interrupt pin, INT0.
The 4000PC has INT0 through INT5 pins.  We assume that in the case of the
I/O ASIC's interval timer, the INT4 pin of the cpu is tied to the I/O ASIC,
and accessing the IT_STAT register clears the pending interrupt by lowering
the pin.  All is well on the 4000PC.

Not so on the 4000SC.  We only have one interrupt pin, INT0.  For other
interrupts, an external write request by the I/O ASIC to the cpu's SysAD
bus at a specific address provides access to the transparent interrupt
register, which allows the device to raise interrupts that don't have dedicated
cpu pins.  The problem is that simply accessing the IT_STAT register on the
ASIC is sadly not enough to clear the pending INT4 on a 4000SC.  We end up
getting caught in a tight loop when calling _splnone(), since the pending INT4
is never being cleared in the clkintr handler.  So the question remains, how
do we clear this pending INT4???  I'm going to try calling Mips again tomorrow,
hopefully I can find the answer.  The Mips R4000 User's Manual was not helpful
in this specific area.  If ANYONE reading this has any info, please let me 
know.

Cheers,
-Mark