On Tue, 28 Sep 2004, Gunther Nikl wrote:
>
>   Ah, I see. Thats what I wanted to know. Sparc64 can only write a lw to
>   a lw-aligned address?

  Specifically, SPARCv9 machines require ALL data accesses to be aligned,
i.e. halfword must be 2-byte-aligned, words 4-byte-aligned, longwords
("extended word" seems to be the SPARCv9 term) 8-byte-aligned and
quadwords 16-byte-aligned.

  A theoretical exception are double-precision floats, in which case it's
(hardware-)implementation dependent whether the memory address must be 4-
or 8-byte aligned, but at least SUN UltraSPARC-I CPUs (and I assume later)
do generate a FP_mem_not_aligned_trap for <64bit aligned addresses.

  I suspect these alignment restrictions would be true for just about any
CPU which calls itself RISC.

-- 
/ali
:wq