Port-amd64 archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

Re: dropping d=1 w=0



On Sat, Feb 29, 2020 at 08:43:40PM +0000, Andrew Doran wrote:

> On Sat, Feb 29, 2020 at 07:47:17AM +0100, Maxime Villard wrote:
> 
> > Le 28/02/2020 ? 19:51, is%netbsd.org@localhost a ?crit?:
> > > On Fri, Feb 28, 2020 at 07:14:47PM +0100, Maxime Villard wrote:
> > >> We need to eliminate the pages that have the "dirty" bit set without the
> > >> "writable" bit set.
> > >>
> > >> The biggest cause of these pages is pmap_write_protect(), which drops
> > >> PTE_W but leaves PTE_D.
> > > 
> > > Is this a bug or intentional? - as  in
> > > "no more changes here, but need still to write what was changed earlier"
> > 
> > Actually, I'm not so sure now. Maybe UVM will have to be fixed too.
> 
> I think you probably just need a change in pmap_write_protect() to copy D
> into pp_attrs if pmap_pv_tracked() gives you a non-NULL page, no?  Then
> you'd be fine to clear D on the PTE.

Oops - I mean if PTE_PVLIST is set on the PTE.  Because if it's not a
managed mapping, then UVM doesn't care about the dirty bit.

Andrew

> Andrew
> 
> > The reason is that the combination of d=1 and w=0 will have a new meaning
> > on future x86 CPUs, which will have nothing to do with actual dirtiness
> > and readonlyness.


Home | Main Index | Thread Index | Old Index