Le mar. 11 déc. 2018 à 23:41, Jaromír Doleček
<jaromir.dolecek%gmail.com@localhost> a écrit :
I'm investigating an initial solution which will keep the
ipending+ilevel still as 64-bit quantity suitable for cmpxchg8b, using
4 bits for the ilevel and remaining 60 for ipending.
I have some intermediary code which compiles, but likely not yet works
(not tested yet):
https://www.netbsd.org/~jdolecek/x86_intr_cpu56.diff
I went for for 8/56 split for ilevel/ipending, because it makes the
coding way more convenient - no masks and shifts necessary, can fetch
ilevel with just 'movb' and then the whole thing with 'movq'.
In IDTVEC() I've replaced
orl $(1 << num),CPUVAR(IPENDING)
with
btsq $(num),CPUVAR(...)
since 'orq' doesn't support 64-bit immediate argument. For zeroing the
top 8bit for ipending I've used 'andq' with mask in register.
I've replaced the atomic_and_32() in intr.c with just membar_sync()
before and after, so that the code doesn't need 64-bit atomic ops. In
fact I'm not really convinced it's necessary at all - the code
disables all interrupts before executing this, so perhaps the
synchronization is not needed at all?
Jaromir