Re: PCID support for amd64 - initial patch.

[Jaromír Doleček <jaromir.dolecek%gmail.com@localhost>]

Hello,

I've fixed the remaining issues WRT SVS, so the current version boots
and works without apparent problems with and without SVS. I tested
this inside emulator with PCID/INVPCID support.

Patch:
http://www.netbsd.org/~jdolecek/pcid_support+svs.diff

This version is probably close to what will eventually get integrated.
First I want to confirm the functionality on real hardware, and check
what kind of performance difference does it make for both SVS and
non-SVS case. I'll share results once I'll have them.

Jaromir


2018-03-09 22:36 GMT+01:00 Jaromír Doleček <jaromir.dolecek%gmail.com@localhost>:
> Hello,
>
> I've made updated patch, done against -current tree after the unrelated
> refactorings were committed separately.
>
> This version was already updated and tested with SVS, but support is not
> complete yet. When I disable TLB flush on switch from kernel to user address
> space, programs (e.g. single user shell) SIGSEGV. The patch however already
> avoids TLB flush on switch from user to kernel address space.
>
> Stay tuned.
>
> The patch is available at:
> https://drive.google.com/file/d/1MSZVIcAgluhxLGwS62Of1Ev-q5zepFS7/view?usp=sharing
>
> Jaromir
>
> 2018-03-03 21:46 GMT+01:00 Jaromír Doleček <jaromir.dolecek%gmail.com@localhost>:
>>
>> Hello,
>>
>> here is a patch to implement initial PCID support for amd64. This feature
>> is available on recent Intel processors, starting with Haswell, and
>> optimises TLB use during address space switch.
>>
>> The patch compiles and seems to work fine in emulator, but I haven't
>> tested it with real hardware just yet. I should be able to do so in a week
>> or so. By then I'd also see if there is any performance improvement. I'm
>> sharing this now just to gather some early feedback.
>>
>> It only activates when both PCID and INVPCID is supported by boot
>> processor. I think it's not worth the efford any more to try supporting the
>> early machines with PCID but without INVPCID.
>>
>> I've considered using the MI pmap_tlb.c ASID code and evaluated sparc64
>> CTX and alpha ASN counterparts. Opted to use sparc64 pmap approach for
>> simplicity and similar features (12 bits context space compared to sparc
>> 13+), on the end I however actually used pretty much the alpha approach.
>> It's using just a generation number for invalidation on ASID wraparound,
>> instead of an explicit pmap list like sparc64.
>>
>> There is no support for SVS yet, which was actually the primary driver for
>> this effort. SVS code will need to be modified to not force TLB flushes on
>> address space switch. This will be now the next step for me.
>>
>> Thoughts welcome. I plan to integrate this into the -current tree within
>> couple of weeks.
>>
>> Jaromir
>
>