SPL NOT LOWERED ON TRAP EXIT

[coypu%SDF.ORG@localhost]

Those messages hurt pretty bad when coredumps fail,
filling up the dmesg buffer and messing up the backtrace,
which on a 12-core machine ends up looking like this:
EPRRE DP   O6  0T O
TNR  A 6R6A  00
PI
 TE XIT 0uv6 m0_fault(0xfffffe84745e55e8, 0x0, 1) -> e
fatal page fault in WsAuNeINrGv:i sSoPrL  NmOTo dLOWWAERRNErNDGa:OpN S TtPRyLApPNe O6E  cXoIdO W06 0R
 DriOpN TRfPf fffXfITf 8W60A 2R0N5I8N1G : cSsP L8NOr fLlOaWgs E1R0E2D8 6 Nc rT2R A5P4E XiIleT 6el 08
 rsp fffffe811ddbaac0
curlwp 0xfffffe8467a20a40 pid 305.1 lowest kstack 0WfRfffNIN8G:W ASRPNdIbN 7GN:O2 c 0SLOPWERED  NOOTN  LORAWPE REEXDWTA OR6N  0
T: SRPALP  EXOITT  6L W0AER

Someone who knows x86 -- is the following diff valid?
global panicstr == NULL if we didn't start panicing
yet. (see kern_assert.c)

Index: amd64_trap.S
===================================================================
RCS file: /cvsroot/src/sys/arch/amd64/amd64/amd64_trap.S,v
retrieving revision 1.4
diff -u -p -u -r1.4 amd64_trap.S
--- amd64_trap.S	7 Aug 2016 09:04:55 -0000	1.4
+++ amd64_trap.S	6 Feb 2017 11:47:30 -0000
@@ -414,6 +414,9 @@ calltrap:
 	jmp	.Lalltraps_checkast	/* re-check ASTs */
 3:	CHECK_DEFERRED_SWITCH
 	jnz	9f
+	movq	%rbx,_C_LABEL(panicstr)
+	cmpq	$0x0,%rbx		/* already in panic */
+	jnz	9f
 #ifndef DIAGNOSTIC
 6:	INTRFASTEXIT
 #else /* DIAGNOSTIC */


I think it works but I'm not sure