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Re: Non power-of-two cache sizes and page colouring

[ See the thread "Non power-of-two cache sizes and page colouring"
  on tech-kern for info leading up to this.  Quick summary is that
  Intel CPUs when booted with amd64 port get cache configuration
  very wrong ]

Simon Burge wrote:

> Izumi Tsutsui wrote:
> > i386/i386/identcpu.c may have the structure for it?
> Ah, intel_cpuid_cache_info[] is exactly what we want, although
> somewhat out of date.

After updating intel_cpuid_cache_info[], here's the difference between
amd64 and i386 output describing the cache info for cpu0:

-cpu0: L2 cache 6 MB 64B/line 16-way
+cpu0: I-cache 32 KB 64B/line 8-way, D-cache 32 KB 64B/line 8-way
+cpu0: L2 cache 6 MB 64B/line 24-way
+cpu0: ITLB 128 4 KB entries 4-way, 256 4 KB entries 4-way
+cpu0: DTLB 16 4 KB entries 4-way, 4K/4M: 16 entries
-cpu0: 96 page colors
+cpu0: 64 page colors

The other differences are how the model is reported:

-cpu0: Intel(R) Xeon(R) CPU           E5420  @ 2.50GHz, 2500.13 MHz

+cpu0: Intel Pentium III (Katmai) (686-class), 2500.15 MHz, id 0x10676
+cpu0: "Intel(R) Xeon(R) CPU           E5420  @ 2.50GHz"

An extra bit in the features mask (B20):

-cpu0: features bffbfbff<PGE,MCA,CMOV,PAT,PSE36,CFLUSH,B20,DS,ACPI,MMX>
+cpu0: features bfebfbff<PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX>

And what looks at first glance to be in incorrect features3 report from
amd64?  Notice same value as "features" above:

-cpu0: features3 bffbfbff<SYSCALL/SYSRET,XD,EM64T>
+cpu0: features3 20100000<XD,EM64T>

> > Should we move it under arch/x86?
> Definitely.  I'll look into this.

So should all of {amd64,i386}/*/identcpu.c be shared under x86?  Or
perhaps we could leave some of the older 486/586 CPU class support under
i386/i386/identcpu.c ...


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