Subject: Re: Inquiring minds want to know.
To: Aaron J. Grier <firstname.lastname@example.org>
From: Nathan J. Williams <email@example.com>
Date: 05/21/2003 17:59:01
"Aaron J. Grier" <firstname.lastname@example.org> writes:
> On Sat, May 17, 2003 at 11:15:08PM +1000, Collin Baillie wrote:
> > I'm wondering if anyone out there can extoll the differences between
> > the Alpha 64-bitness and the new Opterons. I know the opteron is a
> > glorified x86 box, but how does it stack up (theroetically) against
> > the Alpha?
> I'm curious about this, too. I seem to recall that AMD used some of the
> same bus interfacing that Alpha did.
For the Athlon, AMD actually used the same bus that the Alpha did for
their current generation; for the Opteron, AMD used a very similar
architecture, but with a different specific protocol.
The Athlon used a bus that matched that of the Alpha 21264 (EV6):
point-to-point between the CPUs and a system controller that also
connected to the memory and device buses. The Opteron and Alpha 21364
(EV7) both use an arrangement where each CPU has a memory controller
and several point-to-point interprocessor links. In the case of the
Opteron, each CPU has three HyperTransport links; in the case of the
21364, each CPU has four links, apparantly without a trendy name. The
Opteron currently supports up to eight processors, and the
HyperTransport routing table is flexible enough for them to be
arranged in a number of different ways. The 21364 supports up to 128
processors, and the intent is to arrange them in a 2-D torus. The
21364's packet router is a bit more flexible at runtime and can make
use of different paths through the grid to increase bandwidth between
So both the 21364 and the Opteron are designed to be cache-coherent
non-uniform memory multiprocessing systems (ccNUMA) with a minimum of
glue logic. The Opteron would appear to have more promise of bringing
this style of multiprocessing to the hobbyist desktop or server