Subject: Re: NEW_SCC_DRIVER problem
To: Jason R Thorpe <firstname.lastname@example.org>
From: Bill Studenmund <email@example.com>
Date: 11/06/2000 14:17:27
On Sun, 5 Nov 2000, Jason R Thorpe wrote:
> > This means channel A and B is _not_ independent.
> It's true of all TC Alphas and the TC DECstations that have the SCC
> chip, as well. In fact, it's because we currently don't handle the
> cross-wiring of the devices that the NEW_SCC_DRIVER is not the default.
> Bill Studenmund and I had some ideas on how to fix the problem, but we
> changed jobs before we had a chance to implement them. I need to get
> my 3000/300 set up so we can work on it again.
Yes. My idea was to teach the MI driver that DTR & RTS might be on a
different channel from the rest of the chip. We then seperate the code in
the MI zstty driver so that reads & writes of r5 which are for DTR & RTS
are seperate from those for the other bits (only matters heavily in
Then we add an extra zsc_attach_args option which says which hardware
channel to use for DTR & RTS (say hfcchannel). Most attachers (everyting
other than alpha and pmax) will have it be the same thing as the channel
for the rest of the tty. But pmax and alpha will have it point to the
Then we have zst_cs and zst_cs_hfc. The latter is the struct zs_chanstate
* which is used for DTR & RTS.
That should do it.