Subject: Re: DPWS500/Pyxis bugs, corrupt memory etc.
To: Andrew Gallatin <gallatin@cs.duke.edu>
From: Manuel Bouyer <bouyer@antioche.lip6.fr>
List: port-alpha
Date: 02/05/2000 14:38:36
On Fri, Feb 04, 2000 at 08:39:11PM -0500, Andrew Gallatin wrote:
> [...]
> I asked our ATA driver author about the page-crossing bug & he tells
> me that all ATA accesses are at max one page, and always page aligned.
> And that the chip should not combine multiple transactions if their
> DMA addresses are physically contiguous.
> 
> Unless this information is in error or the NetBSD driver does
> something clever & combines transactions so that they are > PAGE_SIZE,
> I'm not sure where the original poster's IDE corruption is coming
> from.

NetBSD does combine transactions, it's probably the problem for this machine.
Something can certainly be done at the bus_dma level to work around it
(forcing transactions <= PAGE_SIZE).

--
Manuel Bouyer <bouyer@antioche.eu.org>
--