Subject: Re: linear and non-cacheable mapping vs bwx
To: Chris G. Demetriou <firstname.lastname@example.org>
From: Matthias Drochner <email@example.com>
Date: 09/03/1999 15:02:06
> Linear access should only be allowed if the region behaves like memory
> from the kernel's point of view.
Well - it _is_ memory in the particular case I had
to deal with (the if_ti driver).
It is shared memory between the adapter's CPU and PCI.
So far it can be write-combined and prefetched as long
as memory barriers are used where needed to get coherence.
> and devmem is prefetchable (what the code means by cacheable there,
There is the problem: We can't express these "in-betweens".
The other way would be to map the range as "cacheable" from
the device driver (even if this bit is not set in the
PCI config register (*)).
But that's not right either - the mapping needs memory barriers
just like other device memory, not more. "Cacheable" would
mean for me that the md code is free to put it behind
a real cache, so cache flushes would be needed for coherence.
(*) Just had a look at the PCI specs - this bit is called
"prefetchable", and it is explicitely stated that this
memory is _not_ to be cached by the host CPU. So I guess
this bit should have been set in the BAR.
So it just becoming clear that "prefetchable" and "cacheable"
are different things and should get separate flag bits...