CVS commit: wip/verilog08

["Makoto Fujiwara" <makoto%users.sourceforge.net@localhost>]

Module name:    wip
Committed by:   makoto
Date:           Wed Aug 20 11:37:00 UTC 2014

Added Files:
        wip/verilog08: DESCR Makefile PLIST TODO buildlink3.mk distinfo
        wip/verilog08/patches: patch-ad patch-cadpli_Makefile_in
            patch-driver-vpi_Makefile_in patch-driver_Makefile_in
            patch-elab__net_cc patch-ivlpp_Makefile_in
            patch-libveriuser_Makefile_in patch-tgt-edif_Makefile_in
            patch-tgt-fpga_Makefile_in patch-tgt-null_Makefile_in
            patch-tgt-pal_Makefile_in patch-tgt-stub_Makefile_in
            patch-tgt-verilog_Makefile_in patch-vpi_Makefile_in
            patch-vvp_Makefile_in

Log Message:
Import verilog08-0.8.7 as wip/verilog08.
Verilog 0.8 revived. Newer version said dropped the synthesis capability.
(This version was picked up 2009-03 of cad/verilog and added user-destdir
patches)

Verilog-0.8 series has synthesize capability to xnf (Xilinx)  and fpga(EDIF).

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
compiler, compiling source code writen in Verilog (IEEE-1364) into some target
format. For batch simulation, the compiler can generate C++ code that is
compiled and linked with a run time library (called "vvm") then executed as
a command to run the simulation. For synthesis, the compiler generates
netlists in the desired format.

The compiler proper is intended to parse and elaborate design descriptions
written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
complex standard, so it will take some time for it to get there, but that's
the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well,
and some -1999 features will creep in.

To generate a diff of this commit:
cvs -z3 rdiff -u -r0 -r1.1 wip/verilog08/DESCR wip/verilog08/Makefile \
    wip/verilog08/PLIST wip/verilog08/TODO wip/verilog08/buildlink3.mk \
    wip/verilog08/distinfo wip/verilog08/patches/patch-ad \
    wip/verilog08/patches/patch-cadpli_Makefile_in \
    wip/verilog08/patches/patch-driver-vpi_Makefile_in \
    wip/verilog08/patches/patch-driver_Makefile_in \
    wip/verilog08/patches/patch-elab__net_cc \
    wip/verilog08/patches/patch-ivlpp_Makefile_in \
    wip/verilog08/patches/patch-libveriuser_Makefile_in \
    wip/verilog08/patches/patch-tgt-edif_Makefile_in \
    wip/verilog08/patches/patch-tgt-fpga_Makefile_in \
    wip/verilog08/patches/patch-tgt-null_Makefile_in \
    wip/verilog08/patches/patch-tgt-pal_Makefile_in \
    wip/verilog08/patches/patch-tgt-stub_Makefile_in \
    wip/verilog08/patches/patch-tgt-verilog_Makefile_in \
    wip/verilog08/patches/patch-vpi_Makefile_in \
    wip/verilog08/patches/patch-vvp_Makefile_in

To view a diff of this commit:
http://pkgsrc-wip.cvs.sourceforge.net/pkgsrc-wip/wip/verilog08/DESCR?r1=0&r2=1.1
http://pkgsrc-wip.cvs.sourceforge.net/pkgsrc-wip/wip/verilog08/Makefile?r1=0&r2=1.1
http://pkgsrc-wip.cvs.sourceforge.net/pkgsrc-wip/wip/verilog08/PLIST?r1=0&r2=1.1
http://pkgsrc-wip.cvs.sourceforge.net/pkgsrc-wip/wip/verilog08/TODO?r1=0&r2=1.1
http://pkgsrc-wip.cvs.sourceforge.net/pkgsrc-wip/wip/verilog08/buildlink3.mk?r1=0&r2=1.1
http://pkgsrc-wip.cvs.sourceforge.net/pkgsrc-wip/wip/verilog08/distinfo?r1=0&r2=1.1
http://pkgsrc-wip.cvs.sourceforge.net/pkgsrc-wip/wip/verilog08/patches/patch-ad?r1=0&r2=1.1
http://pkgsrc-wip.cvs.sourceforge.net/pkgsrc-wip/wip/verilog08/patches/patch-cadpli_Makefile_in?r1=0&r2=1.1
http://pkgsrc-wip.cvs.sourceforge.net/pkgsrc-wip/wip/verilog08/patches/patch-driver-vpi_Makefile_in?r1=0&r2=1.1
http://pkgsrc-wip.cvs.sourceforge.net/pkgsrc-wip/wip/verilog08/patches/patch-driver_Makefile_in?r1=0&r2=1.1
http://pkgsrc-wip.cvs.sourceforge.net/pkgsrc-wip/wip/verilog08/patches/patch-elab__net_cc?r1=0&r2=1.1
http://pkgsrc-wip.cvs.sourceforge.net/pkgsrc-wip/wip/verilog08/patches/patch-ivlpp_Makefile_in?r1=0&r2=1.1
http://pkgsrc-wip.cvs.sourceforge.net/pkgsrc-wip/wip/verilog08/patches/patch-libveriuser_Makefile_in?r1=0&r2=1.1
http://pkgsrc-wip.cvs.sourceforge.net/pkgsrc-wip/wip/verilog08/patches/patch-tgt-edif_Makefile_in?r1=0&r2=1.1
http://pkgsrc-wip.cvs.sourceforge.net/pkgsrc-wip/wip/verilog08/patches/patch-tgt-fpga_Makefile_in?r1=0&r2=1.1
http://pkgsrc-wip.cvs.sourceforge.net/pkgsrc-wip/wip/verilog08/patches/patch-tgt-null_Makefile_in?r1=0&r2=1.1
http://pkgsrc-wip.cvs.sourceforge.net/pkgsrc-wip/wip/verilog08/patches/patch-tgt-pal_Makefile_in?r1=0&r2=1.1
http://pkgsrc-wip.cvs.sourceforge.net/pkgsrc-wip/wip/verilog08/patches/patch-tgt-stub_Makefile_in?r1=0&r2=1.1
http://pkgsrc-wip.cvs.sourceforge.net/pkgsrc-wip/wip/verilog08/patches/patch-tgt-verilog_Makefile_in?r1=0&r2=1.1
http://pkgsrc-wip.cvs.sourceforge.net/pkgsrc-wip/wip/verilog08/patches/patch-vpi_Makefile_in?r1=0&r2=1.1
http://pkgsrc-wip.cvs.sourceforge.net/pkgsrc-wip/wip/verilog08/patches/patch-vvp_Makefile_in?r1=0&r2=1.1

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

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