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rust197: add patches so that this works on NetBSD/aarch64eb again.
Module Name: pkgsrc-wip
Committed By: Havard Eidnes <he%NetBSD.org@localhost>
Pushed By: he
Date: Sun Jul 26 09:59:58 2026 +0000
Changeset: 4d822507d215f99ac7420a2668ff2e6c8a175348
Modified Files:
rust197/Makefile
rust197/distinfo
rust197/patches/patch-vendor_memchr-2.7.4_src_vector.rs
Added Files:
rust197/patches/patch-vendor_memchr-2.7.2_src_vector.rs
rust197/patches/patch-vendor_memchr-2.7.5_src_vector.rs
rust197/patches/patch-vendor_memchr-2.7.6_src_vector.rs
rust197/patches/patch-vendor_memchr-2.8.0_src_vector.rs
Log Message:
rust197: add patches so that this works on NetBSD/aarch64eb again.
Pkgsrc changes:
* Add patches to the newer memchr crates so that it also
works on big-endian aarch64.
Patch from https://github.com/BurntSushi/memchr/pull/222,
fixes https://github.com/rust-lang/rust/issues/159919.
(So eventually these patches may be removed once the older
memchr crates are retired by the rust compiler.)
* Checksums + checksum substitutions.
To see a diff of this commit:
https://wip.pkgsrc.org/cgi-bin/gitweb.cgi?p=pkgsrc-wip.git;a=commitdiff;h=4d822507d215f99ac7420a2668ff2e6c8a175348
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
diffstat:
rust197/Makefile | 9 ++++++
rust197/distinfo | 6 +++-
.../patch-vendor_memchr-2.7.2_src_vector.rs | 34 ++++++++++++++++++++++
.../patch-vendor_memchr-2.7.4_src_vector.rs | 30 +++++++++++++++++++
.../patch-vendor_memchr-2.7.5_src_vector.rs | 34 ++++++++++++++++++++++
.../patch-vendor_memchr-2.7.6_src_vector.rs | 34 ++++++++++++++++++++++
.../patch-vendor_memchr-2.8.0_src_vector.rs | 34 ++++++++++++++++++++++
7 files changed, 180 insertions(+), 1 deletion(-)
diffs:
diff --git a/rust197/Makefile b/rust197/Makefile
index 56cc431e2f..55aa7d74a5 100644
--- a/rust197/Makefile
+++ b/rust197/Makefile
@@ -558,6 +558,15 @@ CKSUMS+= 28d66e566b73f6f0f7add4092874dc967ce133bfb6dcbd81f03c9a04b6e4e1d0
CKSUMS+= 44cd1a614bd66f1e66fc86c541d3c3b8d3a14a644c13e8bf816df3f555eac2d4
CKSUMS+= 27f9bff08b24828e1a611b10a0282f5457d12e9e7254202040144d392297d720
+CKSUM_CRATES+= vendor/memchr-2.7.6
+CKSUMS+= e787c4ed2f499802e90910f7aedc7ca41acea39c8ef416b19d6d572c1a540422
+CKSUMS+= 9b104d0bda9b8e18b10c41633513637af84346282bf113f3be3813725605fe31
+
+CKSUM_CRATES+= vendor/memchr-2.8.0
+# Covered by memchr-2.7.6 above
+#CKSUMS+= e787c4ed2f499802e90910f7aedc7ca41acea39c8ef416b19d6d572c1a540422
+#CKSUMS+= 9b104d0bda9b8e18b10c41633513637af84346282bf113f3be3813725605fe31
+
CKSUM_CRATES+= vendor/line-index-0.1.2
CKSUMS+= c4613b718951cf0b880a3a7829e102a9ec7196591437e3bc0cfd857c717bfb61
CKSUMS+= 5183e802793932fb980b4e321656c65d1b6231de3febd1ac94dfa73de31245f0
diff --git a/rust197/distinfo b/rust197/distinfo
index 3080254522..6c588c0497 100644
--- a/rust197/distinfo
+++ b/rust197/distinfo
@@ -167,11 +167,15 @@ SHA1 (patch-vendor_libc-0.2.186_src_unix_bsd_netbsdlike_netbsd_m68k.rs) = f87afd
SHA1 (patch-vendor_libc-0.2.186_src_unix_bsd_netbsdlike_netbsd_mod.rs) = df252ac69c390d1931d48f446b2b892b2c954f9e
SHA1 (patch-vendor_line-index-0.1.2_src_lib.rs) = 30aa5c82630ea0e8969abb527c11640712efba1e
SHA1 (patch-vendor_lzma-sys-0.1.20_config.h) = 4849052ddb2f04f539fd7060fc1b43cc3acf99c4
+SHA1 (patch-vendor_memchr-2.7.2_src_vector.rs) = 28007f46c3660a7f26a8dbdbbca936dfac2c216c
SHA1 (patch-vendor_memchr-2.7.4_src_arch_aarch64_memchr.rs) = 3e17e9f068afe5e812d10bf57fd3f6d4c21baf0b
SHA1 (patch-vendor_memchr-2.7.4_src_arch_aarch64_mod.rs) = 24bbd69c8b571e5652d5306989b6598b58ec1966
SHA1 (patch-vendor_memchr-2.7.4_src_memchr.rs) = 4c2f4fa4911f38acd3b36c311abd14d3c9751672
SHA1 (patch-vendor_memchr-2.7.4_src_memmem_searcher.rs) = a5038873015004ab0c8769dda84edc16a9c55f24
-SHA1 (patch-vendor_memchr-2.7.4_src_vector.rs) = 50a901d061cf58a745b0c387a1c45ff2f0c54e89
+SHA1 (patch-vendor_memchr-2.7.4_src_vector.rs) = ceb9f4bcfa1701276966eba22145f54b1f6142cc
+SHA1 (patch-vendor_memchr-2.7.5_src_vector.rs) = fb1a33c4150f9897c049cbea29d375b57d0bd684
+SHA1 (patch-vendor_memchr-2.7.6_src_vector.rs) = 5289c3ebf1a34409106d44eda96936f06c1312bb
+SHA1 (patch-vendor_memchr-2.8.0_src_vector.rs) = f7cb9435e46bbb8ad7c1f3ce980279e75e5fa725
SHA1 (patch-vendor_openssl-src-111.28.2+1.1.1w_openssl_Configurations_10-main.conf) = 8fc746574f16cd3294edce99beffc3e8c03a089b
SHA1 (patch-vendor_openssl-src-111.28.2+1.1.1w_openssl_crypto_aria_aria.c) = 1373d2e4ab609956e0e51ca3d900861caf3ee70d
SHA1 (patch-vendor_openssl-src-111.28.2+1.1.1w_src_lib.rs) = c3260bfdd670c31845189fcb6b4ed19385a03b2a
diff --git a/rust197/patches/patch-vendor_memchr-2.7.2_src_vector.rs b/rust197/patches/patch-vendor_memchr-2.7.2_src_vector.rs
new file mode 100644
index 0000000000..3f4e734a81
--- /dev/null
+++ b/rust197/patches/patch-vendor_memchr-2.7.2_src_vector.rs
@@ -0,0 +1,34 @@
+$NetBSD$
+
+Apply fix for big-endian aarch64 from
+https://github.com/BurntSushi/memchr/pull/222
+
+--- vendor/memchr-2.7.2/src/vector.rs.orig 2026-07-14 15:13:08.000000000 +0000
++++ vendor/memchr-2.7.2/src/vector.rs
+@@ -324,6 +324,7 @@ mod aarch64neon {
+ }
+
+ #[inline(always)]
++ #[cfg(target_endian = "little")]
+ unsafe fn movemask(self) -> NeonMoveMask {
+ let asu16s = vreinterpretq_u16_u8(self);
+ let mask = vshrn_n_u16(asu16s, 4);
+@@ -333,6 +334,18 @@ mod aarch64neon {
+ }
+
+ #[inline(always)]
++ #[cfg(target_endian = "big")]
++ unsafe fn movemask(self) -> NeonMoveMask {
++ // Swap the endianness of each 16-bit input.
++ let asu16s = vreinterpretq_u16_u8(vrev16q_u8(self));
++ let mask = vshrn_n_u16(asu16s, 4);
++ let asu64 = vreinterpret_u64_u8(mask);
++ // Use `swap_bytes` to swap the endianness of the 64-bit output.
++ let scalar64 = vget_lane_u64(asu64, 0).swap_bytes();
++ NeonMoveMask(scalar64 & 0x8888888888888888)
++ }
++
++ #[inline(always)]
+ unsafe fn cmpeq(self, vector2: Self) -> uint8x16_t {
+ vceqq_u8(self, vector2)
+ }
diff --git a/rust197/patches/patch-vendor_memchr-2.7.4_src_vector.rs b/rust197/patches/patch-vendor_memchr-2.7.4_src_vector.rs
index a778790a6b..af83479327 100644
--- a/rust197/patches/patch-vendor_memchr-2.7.4_src_vector.rs
+++ b/rust197/patches/patch-vendor_memchr-2.7.4_src_vector.rs
@@ -2,6 +2,9 @@ $NetBSD: patch-vendor_memchr-2.7.4_src_vector.rs,v 1.3 2025/08/25 17:51:13 wiz E
Don't try to do neon / SIMD on big-endian aarch64.
+Apply fix for big-endian aarch64 from
+https://github.com/BurntSushi/memchr/pull/222
+
--- vendor/memchr-2.7.4/src/vector.rs.orig 2024-09-22 14:16:06.473207292 +0000
+++ vendor/memchr-2.7.4/src/vector.rs
@@ -289,7 +289,7 @@ mod x86avx2 {
@@ -13,3 +16,30 @@ Don't try to do neon / SIMD on big-endian aarch64.
mod aarch64neon {
use core::arch::aarch64::*;
+@@ -319,6 +319,7 @@ mod aarch64neon {
+ }
+
+ #[inline(always)]
++ #[cfg(target_endian = "little")]
+ unsafe fn movemask(self) -> NeonMoveMask {
+ let asu16s = vreinterpretq_u16_u8(self);
+ let mask = vshrn_n_u16(asu16s, 4);
+@@ -328,6 +329,18 @@ mod aarch64neon {
+ }
+
+ #[inline(always)]
++ #[cfg(target_endian = "big")]
++ unsafe fn movemask(self) -> NeonMoveMask {
++ // Swap the endianness of each 16-bit input.
++ let asu16s = vreinterpretq_u16_u8(vrev16q_u8(self));
++ let mask = vshrn_n_u16(asu16s, 4);
++ let asu64 = vreinterpret_u64_u8(mask);
++ // Use `swap_bytes` to swap the endianness of the 64-bit output.
++ let scalar64 = vget_lane_u64(asu64, 0).swap_bytes();
++ NeonMoveMask(scalar64 & 0x8888888888888888)
++ }
++
++ #[inline(always)]
+ unsafe fn cmpeq(self, vector2: Self) -> uint8x16_t {
+ vceqq_u8(self, vector2)
+ }
diff --git a/rust197/patches/patch-vendor_memchr-2.7.5_src_vector.rs b/rust197/patches/patch-vendor_memchr-2.7.5_src_vector.rs
new file mode 100644
index 0000000000..a02f6a5464
--- /dev/null
+++ b/rust197/patches/patch-vendor_memchr-2.7.5_src_vector.rs
@@ -0,0 +1,34 @@
+$NetBSD$
+
+Apply fix for big-endian aarch64 from
+https://github.com/BurntSushi/memchr/pull/222
+
+--- vendor/memchr-2.7.5/src/vector.rs.orig 2026-07-14 15:13:08.000000000 +0000
++++ vendor/memchr-2.7.5/src/vector.rs
+@@ -319,6 +319,7 @@ mod aarch64neon {
+ }
+
+ #[inline(always)]
++ #[cfg(target_endian = "little")]
+ unsafe fn movemask(self) -> NeonMoveMask {
+ let asu16s = vreinterpretq_u16_u8(self);
+ let mask = vshrn_n_u16(asu16s, 4);
+@@ -328,6 +329,18 @@ mod aarch64neon {
+ }
+
+ #[inline(always)]
++ #[cfg(target_endian = "big")]
++ unsafe fn movemask(self) -> NeonMoveMask {
++ // Swap the endianness of each 16-bit input.
++ let asu16s = vreinterpretq_u16_u8(vrev16q_u8(self));
++ let mask = vshrn_n_u16(asu16s, 4);
++ let asu64 = vreinterpret_u64_u8(mask);
++ // Use `swap_bytes` to swap the endianness of the 64-bit output.
++ let scalar64 = vget_lane_u64(asu64, 0).swap_bytes();
++ NeonMoveMask(scalar64 & 0x8888888888888888)
++ }
++
++ #[inline(always)]
+ unsafe fn cmpeq(self, vector2: Self) -> uint8x16_t {
+ vceqq_u8(self, vector2)
+ }
diff --git a/rust197/patches/patch-vendor_memchr-2.7.6_src_vector.rs b/rust197/patches/patch-vendor_memchr-2.7.6_src_vector.rs
new file mode 100644
index 0000000000..20170e2611
--- /dev/null
+++ b/rust197/patches/patch-vendor_memchr-2.7.6_src_vector.rs
@@ -0,0 +1,34 @@
+$NetBSD$
+
+Apply fix for big-endian aarch64 from
+https://github.com/BurntSushi/memchr/pull/222
+
+--- vendor/memchr-2.7.6/src/vector.rs.orig 2026-07-14 15:13:08.000000000 +0000
++++ vendor/memchr-2.7.6/src/vector.rs
+@@ -319,6 +319,7 @@ mod aarch64neon {
+ }
+
+ #[inline(always)]
++ #[cfg(target_endian = "little")]
+ unsafe fn movemask(self) -> NeonMoveMask {
+ let asu16s = vreinterpretq_u16_u8(self);
+ let mask = vshrn_n_u16(asu16s, 4);
+@@ -328,6 +329,18 @@ mod aarch64neon {
+ }
+
+ #[inline(always)]
++ #[cfg(target_endian = "big")]
++ unsafe fn movemask(self) -> NeonMoveMask {
++ // Swap the endianness of each 16-bit input.
++ let asu16s = vreinterpretq_u16_u8(vrev16q_u8(self));
++ let mask = vshrn_n_u16(asu16s, 4);
++ let asu64 = vreinterpret_u64_u8(mask);
++ // Use `swap_bytes` to swap the endianness of the 64-bit output.
++ let scalar64 = vget_lane_u64(asu64, 0).swap_bytes();
++ NeonMoveMask(scalar64 & 0x8888888888888888)
++ }
++
++ #[inline(always)]
+ unsafe fn cmpeq(self, vector2: Self) -> uint8x16_t {
+ vceqq_u8(self, vector2)
+ }
diff --git a/rust197/patches/patch-vendor_memchr-2.8.0_src_vector.rs b/rust197/patches/patch-vendor_memchr-2.8.0_src_vector.rs
new file mode 100644
index 0000000000..b31bf7998c
--- /dev/null
+++ b/rust197/patches/patch-vendor_memchr-2.8.0_src_vector.rs
@@ -0,0 +1,34 @@
+$NetBSD$
+
+Apply fix for big-endian aarch64 from
+https://github.com/BurntSushi/memchr/pull/222
+
+--- vendor/memchr-2.8.0/src/vector.rs.orig 2026-07-25 19:57:37.417022627 +0000
++++ vendor/memchr-2.8.0/src/vector.rs
+@@ -319,6 +319,7 @@ mod aarch64neon {
+ }
+
+ #[inline(always)]
++ #[cfg(target_endian = "little")]
+ unsafe fn movemask(self) -> NeonMoveMask {
+ let asu16s = vreinterpretq_u16_u8(self);
+ let mask = vshrn_n_u16(asu16s, 4);
+@@ -328,6 +329,18 @@ mod aarch64neon {
+ }
+
+ #[inline(always)]
++ #[cfg(target_endian = "big")]
++ unsafe fn movemask(self) -> NeonMoveMask {
++ // Swap the endianness of each 16-bit input.
++ let asu16s = vreinterpretq_u16_u8(vrev16q_u8(self));
++ let mask = vshrn_n_u16(asu16s, 4);
++ let asu64 = vreinterpret_u64_u8(mask);
++ // Use `swap_bytes` to swap the endianness of the 64-bit output.
++ let scalar64 = vget_lane_u64(asu64, 0).swap_bytes();
++ NeonMoveMask(scalar64 & 0x8888888888888888)
++ }
++
++ #[inline(always)]
+ unsafe fn cmpeq(self, vector2: Self) -> uint8x16_t {
+ vceqq_u8(self, vector2)
+ }
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