yosys-devel: created to track latest developments in yosys

To: pkgsrc-wip-changes%NetBSD.org@localhost
Subject: yosys-devel: created to track latest developments in yosys
From: mayuresh (via pkgsrc-wip) <commit-notify%pkgsrc.org@localhost>
Date: Thu, 12 Dec 2024 15:58:29 +0000
Module Name:	pkgsrc-wip
Committed By:	mayuresh <mayuresh%acm.org@localhost>
Pushed By:	mayuresh
Date:		Thu Dec 12 21:11:24 2024 +0530
Changeset:	2b659146c856e99883002dad4dee683c1a189929

Added Files:
	yosys-dev/COMMIT_MSG
	yosys-dev/DESCR
	yosys-dev/Makefile
	yosys-dev/PLIST
	yosys-dev/distinfo
	yosys-dev/patches/patch-Makefile
	yosys-dev/patches/patch-kernel_driver.cc

Log Message:
yosys-devel: created to track latest developments in yosys

To see a diff of this commit:
https://wip.pkgsrc.org/cgi-bin/gitweb.cgi?p=pkgsrc-wip.git;a=commitdiff;h=2b659146c856e99883002dad4dee683c1a189929

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

diffstat:
 yosys-dev/COMMIT_MSG                     |   5 +
 yosys-dev/DESCR                          |   3 +
 yosys-dev/Makefile                       |  82 ++++++++
 yosys-dev/PLIST                          | 320 +++++++++++++++++++++++++++++++
 yosys-dev/distinfo                       |  10 +
 yosys-dev/patches/patch-Makefile         |  42 ++++
 yosys-dev/patches/patch-kernel_driver.cc |  15 ++
 7 files changed, 477 insertions(+)

diffs:
diff --git a/yosys-dev/COMMIT_MSG b/yosys-dev/COMMIT_MSG
new file mode 100644
index 0000000000..6daf543e03
--- /dev/null
+++ b/yosys-dev/COMMIT_MSG
@@ -0,0 +1,5 @@
+devel/yosys: Update to version 0.47
+Update prepared in wip by Mayuresh <mayuresh%acm.org@localhost>
+
+See ChangeLog for details:
+https://github.com/YosysHQ/yosys/releases/tag/v0.47
diff --git a/yosys-dev/DESCR b/yosys-dev/DESCR
new file mode 100644
index 0000000000..b6ab21ce38
--- /dev/null
+++ b/yosys-dev/DESCR
@@ -0,0 +1,3 @@
+The Yosys Open SYnthesis Suite is a framework for RTL synthesis tools. It
+currently has extensive Verilog-2005 support and provides a basic set of
+synthesis algorithms for various application domains.
diff --git a/yosys-dev/Makefile b/yosys-dev/Makefile
new file mode 100644
index 0000000000..59b5020e2f
--- /dev/null
+++ b/yosys-dev/Makefile
@@ -0,0 +1,82 @@
+# $NetBSD: Makefile,v 1.12 2024/10/22 11:29:50 thorpej Exp $
+
+# XXX Yosys changed their release tag format in 0.45 to just a bare
+# XXX number, sigh.
+YOSYS_VERSION=	0.47
+YOSYS_TAG=	${YOSYS_VERSION}
+ABC_TAG=	yosys-${YOSYS_VERSION}
+ABC_DISTNAME=	abc-${ABC_TAG}
+DISTNAME=	yosys-${YOSYS_TAG}
+CATEGORIES=	devel
+MASTER_SITES=	${MASTER_SITE_GITHUB:=YosysHQ/}
+GITHUB_TAG=	${YOSYS_TAG}
+EXTRACT_SUFX=	.tar.gz		# needed early
+
+MAINTAINER=	thorpej%NetBSD.org@localhost
+HOMEPAGE=	https://github.com/YosysHQ/yosys
+COMMENT=	Yosys Open SYnthesis Suite
+LICENSE=	isc
+
+DEPENDS+=	graphviz-[0-9]*:../../graphics/graphviz
+
+ONLY_FOR_COMPILER=	clang gcc
+USE_LANGUAGES=		c c++
+USE_CXX_FEATURES=	c++17
+GCC_REQD+=		10
+
+.include "../../mk/bsd.prefs.mk"
+.include "../../mk/compiler.mk"
+
+ABC_DISTFILE=	${ABC_DISTNAME}${EXTRACT_SUFX}
+DISTFILES=	${DEFAULT_DISTFILES}
+
+DISTFILES+=		${ABC_DISTFILE}
+SITES.${ABC_DISTFILE}=	-${MASTER_SITE_GITHUB:=YosysHQ/abc/archive/}${ABC_TAG}${EXTRACT_SUFX}
+
+EXTRACT_DIR.${ABC_DISTFILE}=		${WRKSRC}/abc
+EXTRACT_OPTS_TAR.${ABC_DISTFILE}=	--strip-components=1
+
+.if ${CC_VERSION:Mclang*}
+YOSYS_COMPILER=	clang
+.else
+YOSYS_COMPILER=	gcc
+.endif
+
+USE_TOOLS+=	bash
+USE_TOOLS+=	git
+USE_TOOLS+=	gmake
+USE_TOOLS+=	bison
+USE_TOOLS+=	flex
+USE_TOOLS+=	gawk
+USE_TOOLS+=	pkg-config
+
+REPLACE_PYTHON+=	backends/smt2/*.py
+REPLACE_PYTHON+=	docs/source/*.py
+REPLACE_PYTHON+=	passes/pmgen/*.py
+REPLACE_PYTHON+=	techlibs/common/*.py
+REPLACE_PYTHON+=	techlibs/gatemate/*.py
+REPLACE_PYTHON+=	techlibs/gowin/*.py
+REPLACE_PYTHON+=	techlibs/lattice/*.py
+REPLACE_PYTHON+=	techlibs/nexus/*.py
+REPLACE_PYTHON+=	techlibs/xilinx/*.py
+REPLACE_PYTHON+=	tests/bram/*.py
+REPLACE_PYTHON+=	tests/fsm/*.py
+REPLACE_PYTHON+=	tests/opt_share/*.py
+REPLACE_PYTHON+=	tests/realmath/*.py
+REPLACE_PYTHON+=	tests/share/*.py
+REPLACE_PYTHON+=	tests/tools/*.py
+
+REPLACE_BASH+=		misc/yosys-config.in
+
+do-configure:
+	cd ${WRKSRC} && ${MAKE_PROGRAM} config-${YOSYS_COMPILER}
+
+.include "../../lang/python/application.mk"
+.include "../../lang/python/tool.mk"
+.include "../../lang/tcl/buildlink3.mk"
+.include "../../devel/boost-libs/buildlink3.mk"
+.include "../../devel/readline/buildlink3.mk"
+.include "../../devel/libffi/buildlink3.mk"
+.include "../../devel/cxxopts/buildlink3.mk"
+.include "../../mk/dlopen.buildlink3.mk"
+.include "../../mk/bsd.pkg.mk"
diff --git a/yosys-dev/PLIST b/yosys-dev/PLIST
new file mode 100644
index 0000000000..93f0f22056
--- /dev/null
+++ b/yosys-dev/PLIST
@@ -0,0 +1,320 @@
+@comment $NetBSD: PLIST,v 1.3 2024/10/15 01:32:59 thorpej Exp $
+bin/yosys
+bin/yosys-abc
+bin/yosys-config
+bin/yosys-filterlib
+bin/yosys-smtbmc
+bin/yosys-witness
+share/yosys/abc9_map.v
+share/yosys/abc9_model.v
+share/yosys/abc9_unmap.v
+share/yosys/achronix/speedster22i/cells_map.v
+share/yosys/achronix/speedster22i/cells_sim.v
+share/yosys/adff2dff.v
+share/yosys/anlogic/arith_map.v
+share/yosys/anlogic/brams.txt
+share/yosys/anlogic/brams_map.v
+share/yosys/anlogic/cells_map.v
+share/yosys/anlogic/cells_sim.v
+share/yosys/anlogic/eagle_bb.v
+share/yosys/anlogic/lutrams.txt
+share/yosys/anlogic/lutrams_map.v
+share/yosys/cells.lib
+share/yosys/choices/kogge-stone.v
+share/yosys/cmp2lcu.v
+share/yosys/cmp2lut.v
+share/yosys/cmp2softlogic.v
+share/yosys/coolrunner2/cells_counter_map.v
+share/yosys/coolrunner2/cells_latch.v
+share/yosys/coolrunner2/cells_sim.v
+share/yosys/coolrunner2/tff_extract.v
+share/yosys/coolrunner2/xc2_dff.lib
+share/yosys/dff2ff.v
+share/yosys/ecp5/arith_map.v
+share/yosys/ecp5/brams.txt
+share/yosys/ecp5/brams_map.v
+share/yosys/ecp5/cells_bb.v
+share/yosys/ecp5/cells_ff.vh
+share/yosys/ecp5/cells_io.vh
+share/yosys/ecp5/cells_map.v
+share/yosys/ecp5/cells_sim.v
+share/yosys/ecp5/dsp_map.v
+share/yosys/ecp5/latches_map.v
+share/yosys/ecp5/lutrams.txt
+share/yosys/ecp5/lutrams_map.v
+share/yosys/efinix/arith_map.v
+share/yosys/efinix/brams.txt
+share/yosys/efinix/brams_map.v
+share/yosys/efinix/cells_map.v
+share/yosys/efinix/cells_sim.v
+share/yosys/efinix/gbuf_map.v
+share/yosys/fabulous/arith_map.v
+share/yosys/fabulous/cells_map.v
+share/yosys/fabulous/ff_map.v
+share/yosys/fabulous/io_map.v
+share/yosys/fabulous/latches_map.v
+share/yosys/fabulous/prims.v
+share/yosys/fabulous/ram_regfile.txt
+share/yosys/fabulous/regfile_map.v
+share/yosys/gate2lut.v
+share/yosys/gatemate/arith_map.v
+share/yosys/gatemate/brams.txt
+share/yosys/gatemate/brams_init_20.vh
+share/yosys/gatemate/brams_init_40.vh
+share/yosys/gatemate/brams_map.v
+share/yosys/gatemate/cells_bb.v
+share/yosys/gatemate/cells_sim.v
+share/yosys/gatemate/inv_map.v
+share/yosys/gatemate/lut_map.v
+share/yosys/gatemate/lut_tree_cells.genlib
+share/yosys/gatemate/lut_tree_map.v
+share/yosys/gatemate/mul_map.v
+share/yosys/gatemate/mux_map.v
+share/yosys/gatemate/reg_map.v
+share/yosys/gowin/arith_map.v
+share/yosys/gowin/brams.txt
+share/yosys/gowin/brams_map.v
+share/yosys/gowin/cells_map.v
+share/yosys/gowin/cells_sim.v
+share/yosys/gowin/cells_xtra.v
+share/yosys/gowin/lutrams.txt
+share/yosys/gowin/lutrams_map.v
+share/yosys/greenpak4/cells_blackbox.v
+share/yosys/greenpak4/cells_latch.v
+share/yosys/greenpak4/cells_map.v
+share/yosys/greenpak4/cells_sim.v
+share/yosys/greenpak4/cells_sim_ams.v
+share/yosys/greenpak4/cells_sim_digital.v
+share/yosys/greenpak4/cells_sim_wip.v
+share/yosys/greenpak4/gp_dff.lib
+share/yosys/ice40/abc9_model.v
+share/yosys/ice40/arith_map.v
+share/yosys/ice40/brams.txt
+share/yosys/ice40/brams_map.v
+share/yosys/ice40/cells_map.v
+share/yosys/ice40/cells_sim.v
+share/yosys/ice40/dsp_map.v
+share/yosys/ice40/ff_map.v
+share/yosys/ice40/latches_map.v
+share/yosys/ice40/spram.txt
+share/yosys/ice40/spram_map.v
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_time.h
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h
+share/yosys/include/backends/rtlil/rtlil_backend.h
+share/yosys/include/frontends/ast/ast.h
+share/yosys/include/frontends/ast/ast_binding.h
+share/yosys/include/frontends/blif/blifparse.h
+share/yosys/include/kernel/binding.h
+share/yosys/include/kernel/bitpattern.h
+share/yosys/include/kernel/cellaigs.h
+share/yosys/include/kernel/celledges.h
+share/yosys/include/kernel/celltypes.h
+share/yosys/include/kernel/consteval.h
+share/yosys/include/kernel/constids.inc
+share/yosys/include/kernel/cost.h
+share/yosys/include/kernel/drivertools.h
+share/yosys/include/kernel/ff.h
+share/yosys/include/kernel/ffinit.h
+share/yosys/include/kernel/ffmerge.h
+share/yosys/include/kernel/fmt.h
+share/yosys/include/kernel/fstdata.h
+share/yosys/include/kernel/hashlib.h
+share/yosys/include/kernel/json.h
+share/yosys/include/kernel/log.h
+share/yosys/include/kernel/macc.h
+share/yosys/include/kernel/mem.h
+share/yosys/include/kernel/modtools.h
+share/yosys/include/kernel/qcsat.h
+share/yosys/include/kernel/register.h
+share/yosys/include/kernel/rtlil.h
+share/yosys/include/kernel/satgen.h
+share/yosys/include/kernel/scopeinfo.h
+share/yosys/include/kernel/sexpr.h
+share/yosys/include/kernel/sigtools.h
+share/yosys/include/kernel/timinginfo.h
+share/yosys/include/kernel/utils.h
+share/yosys/include/kernel/yosys.h
+share/yosys/include/kernel/yosys_common.h
+share/yosys/include/kernel/yw.h
+share/yosys/include/libs/ezsat/ezminisat.h
+share/yosys/include/libs/ezsat/ezsat.h
+share/yosys/include/libs/fst/fstapi.h
+share/yosys/include/libs/json11/json11.hpp
+share/yosys/include/libs/sha1/sha1.h
+share/yosys/include/passes/fsm/fsmdata.h
+share/yosys/intel/common/altpll_bb.v
+share/yosys/intel/common/brams_m9k.txt
+share/yosys/intel/common/brams_map_m9k.v
+share/yosys/intel/common/ff_map.v
+share/yosys/intel/common/m9k_bb.v
+share/yosys/intel/cyclone10lp/cells_map.v
+share/yosys/intel/cyclone10lp/cells_sim.v
+share/yosys/intel/cycloneiv/cells_map.v
+share/yosys/intel/cycloneiv/cells_sim.v
+share/yosys/intel/cycloneive/cells_map.v
+share/yosys/intel/cycloneive/cells_sim.v
+share/yosys/intel/max10/cells_map.v
+share/yosys/intel/max10/cells_sim.v
+share/yosys/intel_alm/common/abc9_map.v
+share/yosys/intel_alm/common/abc9_model.v
+share/yosys/intel_alm/common/abc9_unmap.v
+share/yosys/intel_alm/common/alm_map.v
+share/yosys/intel_alm/common/alm_sim.v
+share/yosys/intel_alm/common/arith_alm_map.v
+share/yosys/intel_alm/common/bram_m10k.txt
+share/yosys/intel_alm/common/bram_m10k_map.v
+share/yosys/intel_alm/common/dff_map.v
+share/yosys/intel_alm/common/dff_sim.v
+share/yosys/intel_alm/common/dsp_map.v
+share/yosys/intel_alm/common/dsp_sim.v
+share/yosys/intel_alm/common/lutram_mlab.txt
+share/yosys/intel_alm/common/megafunction_bb.v
+share/yosys/intel_alm/common/mem_sim.v
+share/yosys/intel_alm/common/misc_sim.v
+share/yosys/intel_alm/cyclonev/cells_sim.v
+share/yosys/lattice/arith_map_ccu2c.v
+share/yosys/lattice/arith_map_ccu2d.v
+share/yosys/lattice/brams_16kd.txt
+share/yosys/lattice/brams_8kc.txt
+share/yosys/lattice/brams_map_16kd.v
+share/yosys/lattice/brams_map_8kc.v
+share/yosys/lattice/ccu2c_sim.vh
+share/yosys/lattice/ccu2d_sim.vh
+share/yosys/lattice/cells_bb_ecp5.v
+share/yosys/lattice/cells_bb_xo2.v
+share/yosys/lattice/cells_bb_xo3.v
+share/yosys/lattice/cells_bb_xo3d.v
+share/yosys/lattice/cells_ff.vh
+share/yosys/lattice/cells_io.vh
+share/yosys/lattice/cells_map.v
+share/yosys/lattice/cells_sim_ecp5.v
+share/yosys/lattice/cells_sim_xo2.v
+share/yosys/lattice/cells_sim_xo3.v
+share/yosys/lattice/cells_sim_xo3d.v
+share/yosys/lattice/common_sim.vh
+share/yosys/lattice/dsp_map_18x18.v
+share/yosys/lattice/latches_map.v
+share/yosys/lattice/lutrams.txt
+share/yosys/lattice/lutrams_map.v
+share/yosys/microchip/LSRAM.txt
+share/yosys/microchip/LSRAM_map.v
+share/yosys/microchip/arith_map.v
+share/yosys/microchip/brams_defs.vh
+share/yosys/microchip/cells_map.v
+share/yosys/microchip/cells_sim.v
+share/yosys/microchip/polarfire_dsp_map.v
+share/yosys/microchip/uSRAM.txt
+share/yosys/microchip/uSRAM_map.v
+share/yosys/mul2dsp.v
+share/yosys/nanoxplore/arith_map.v
+share/yosys/nanoxplore/brams.txt
+share/yosys/nanoxplore/brams_init.vh
+share/yosys/nanoxplore/brams_map.v
+share/yosys/nanoxplore/cells_bb.v
+share/yosys/nanoxplore/cells_bb_l.v
+share/yosys/nanoxplore/cells_bb_m.v
+share/yosys/nanoxplore/cells_bb_u.v
+share/yosys/nanoxplore/cells_map.v
+share/yosys/nanoxplore/cells_sim.v
+share/yosys/nanoxplore/cells_sim_l.v
+share/yosys/nanoxplore/cells_sim_m.v
+share/yosys/nanoxplore/cells_sim_u.v
+share/yosys/nanoxplore/cells_wrap.v
+share/yosys/nanoxplore/cells_wrap_l.v
+share/yosys/nanoxplore/cells_wrap_m.v
+share/yosys/nanoxplore/cells_wrap_u.v
+share/yosys/nanoxplore/io_map.v
+share/yosys/nanoxplore/latches_map.v
+share/yosys/nanoxplore/rf_init.vh
+share/yosys/nanoxplore/rf_rams_l.txt
+share/yosys/nanoxplore/rf_rams_m.txt
+share/yosys/nanoxplore/rf_rams_map_l.v
+share/yosys/nanoxplore/rf_rams_map_m.v
+share/yosys/nanoxplore/rf_rams_map_u.v
+share/yosys/nanoxplore/rf_rams_u.txt
+share/yosys/nexus/arith_map.v
+share/yosys/nexus/brams.txt
+share/yosys/nexus/brams_map.v
+share/yosys/nexus/cells_map.v
+share/yosys/nexus/cells_sim.v
+share/yosys/nexus/cells_xtra.v
+share/yosys/nexus/dsp_map.v
+share/yosys/nexus/latches_map.v
+share/yosys/nexus/lrams.txt
+share/yosys/nexus/lrams_map.v
+share/yosys/nexus/lutrams.txt
+share/yosys/nexus/lutrams_map.v
+share/yosys/nexus/parse_init.vh
+share/yosys/pmux2mux.v
+share/yosys/python3/smtio.py
+share/yosys/python3/ywio.py
+share/yosys/quicklogic/common/cells_sim.v
+share/yosys/quicklogic/pp3/abc9_map.v
+share/yosys/quicklogic/pp3/abc9_model.v
+share/yosys/quicklogic/pp3/abc9_unmap.v
+share/yosys/quicklogic/pp3/cells_map.v
+share/yosys/quicklogic/pp3/cells_sim.v
+share/yosys/quicklogic/pp3/ffs_map.v
+share/yosys/quicklogic/pp3/latches_map.v
+share/yosys/quicklogic/pp3/lut_map.v
+share/yosys/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
+share/yosys/quicklogic/qlf_k6n10f/arith_map.v
+share/yosys/quicklogic/qlf_k6n10f/bram_types_sim.v
+share/yosys/quicklogic/qlf_k6n10f/brams_map.v
+share/yosys/quicklogic/qlf_k6n10f/brams_sim.v
+share/yosys/quicklogic/qlf_k6n10f/cells_sim.v
+share/yosys/quicklogic/qlf_k6n10f/dsp_final_map.v
+share/yosys/quicklogic/qlf_k6n10f/dsp_map.v
+share/yosys/quicklogic/qlf_k6n10f/dsp_sim.v
+share/yosys/quicklogic/qlf_k6n10f/ffs_map.v
+share/yosys/quicklogic/qlf_k6n10f/libmap_brams.txt
+share/yosys/quicklogic/qlf_k6n10f/libmap_brams_map.v
+share/yosys/quicklogic/qlf_k6n10f/sram1024x18_mem.v
+share/yosys/quicklogic/qlf_k6n10f/ufifo_ctl.v
+share/yosys/sf2/arith_map.v
+share/yosys/sf2/cells_map.v
+share/yosys/sf2/cells_sim.v
+share/yosys/simcells.v
+share/yosys/simlib.v
+share/yosys/smtmap.v
+share/yosys/techmap.v
+share/yosys/xilinx/abc9_model.v
+share/yosys/xilinx/arith_map.v
+share/yosys/xilinx/brams_defs.vh
+share/yosys/xilinx/brams_xc2v.txt
+share/yosys/xilinx/brams_xc2v_map.v
+share/yosys/xilinx/brams_xc3sda.txt
+share/yosys/xilinx/brams_xc3sda_map.v
+share/yosys/xilinx/brams_xc4v.txt
+share/yosys/xilinx/brams_xc4v_map.v
+share/yosys/xilinx/brams_xc5v_map.v
+share/yosys/xilinx/brams_xc6v_map.v
+share/yosys/xilinx/brams_xcu_map.v
+share/yosys/xilinx/brams_xcv.txt
+share/yosys/xilinx/brams_xcv_map.v
+share/yosys/xilinx/cells_map.v
+share/yosys/xilinx/cells_sim.v
+share/yosys/xilinx/cells_xtra.v
+share/yosys/xilinx/ff_map.v
+share/yosys/xilinx/lut_map.v
+share/yosys/xilinx/lutrams_xc5v.txt
+share/yosys/xilinx/lutrams_xc5v_map.v
+share/yosys/xilinx/lutrams_xcu.txt
+share/yosys/xilinx/lutrams_xcv.txt
+share/yosys/xilinx/lutrams_xcv_map.v
+share/yosys/xilinx/mux_map.v
+share/yosys/xilinx/urams.txt
+share/yosys/xilinx/urams_map.v
+share/yosys/xilinx/xc3s_mult_map.v
+share/yosys/xilinx/xc3sda_dsp_map.v
+share/yosys/xilinx/xc4v_dsp_map.v
+share/yosys/xilinx/xc5v_dsp_map.v
+share/yosys/xilinx/xc6s_dsp_map.v
+share/yosys/xilinx/xc7_dsp_map.v
+share/yosys/xilinx/xcu_dsp_map.v
diff --git a/yosys-dev/distinfo b/yosys-dev/distinfo
new file mode 100644
index 0000000000..75bf2fcc59
--- /dev/null
+++ b/yosys-dev/distinfo
@@ -0,0 +1,10 @@
+$NetBSD: distinfo,v 1.6 2024/10/15 01:32:59 thorpej Exp $
+
+BLAKE2s (abc-yosys-0.47.tar.gz) = 267c6776c8320697514966a22e0d0cce8330ffd0a477dc583d31739a2489d32c
+SHA512 (abc-yosys-0.47.tar.gz) = 7327efe99523b74034d8bbe6d3add0d25f4a764b15de6c8abe058451463e18fdf87d8388225f50c7335164e185d8b36aa317cf0826297cbe0cfc69fdb8617fd7
+Size (abc-yosys-0.47.tar.gz) = 6264697 bytes
+BLAKE2s (yosys-0.47.tar.gz) = 7371b62b7320d0349bc8b89d8a0a2b46c7deeaf5a2b47a1e008befea67e77c8b
+SHA512 (yosys-0.47.tar.gz) = d45dc8983fd03687f06e13e9938fb5424c9a297110d670e79d69f821f51e60ce0c19901488b62aeea801c4ff2616166c50386b3f3fb9c03fe655bb50f2ac7b0a
+Size (yosys-0.47.tar.gz) = 3020517 bytes
+SHA1 (patch-Makefile) = db77fa7d0274a1f11290e46ee92dfc80b7d88556
+SHA1 (patch-kernel_driver.cc) = 4b0b0ffd2a7e3757bdf87728460e34831f2075aa
diff --git a/yosys-dev/patches/patch-Makefile b/yosys-dev/patches/patch-Makefile
new file mode 100644
index 0000000000..46b94ec829
--- /dev/null
+++ b/yosys-dev/patches/patch-Makefile
@@ -0,0 +1,42 @@
+$NetBSD: patch-Makefile,v 1.2 2024/10/15 01:32:59 thorpej Exp $
+
+Disable the TCL shenanigans and just assume installed-by-pkgsrc.
+
+--- Makefile.orig	2024-10-09 06:08:00.000000000 +0000
++++ Makefile	2024-10-14 23:30:11.076057503 +0000
+@@ -433,15 +433,17 @@ endif
+ 
+ 
+ ifeq ($(ENABLE_TCL),1)
+-TCL_VERSION ?= tcl$(shell bash -c "tclsh <(echo 'puts [info tclversion]')")
+-ifeq ($(OS), $(filter $(OS),FreeBSD OpenBSD NetBSD))
+-# BSDs usually use tcl8.6, but the lib is named "libtcl86"
+-TCL_INCLUDE ?= /usr/local/include/$(TCL_VERSION)
+-TCL_LIBS ?= -l$(subst .,,$(TCL_VERSION))
+-else
+-TCL_INCLUDE ?= /usr/include/$(TCL_VERSION)
+-TCL_LIBS ?= -l$(TCL_VERSION)
+-endif
++#TCL_VERSION ?= tcl$(shell bash -c "tclsh <(echo 'puts [info tclversion]')")
++#ifeq ($(OS), $(filter $(OS),FreeBSD OpenBSD NetBSD))
++## BSDs usually use tcl8.6, but the lib is named "libtcl86"
++#TCL_INCLUDE ?= /usr/local/include/$(TCL_VERSION)
++#TCL_LIBS ?= -l$(subst .,,$(TCL_VERSION))
++#else
++#TCL_INCLUDE ?= /usr/include/$(TCL_VERSION)
++#TCL_LIBS ?= -l$(TCL_VERSION)
++#endif
++TCL_INCLUDE ?= ${PREFIX}/include
++TCL_LIBS ?= -L ${PREFIX}/lib -ltcl86
+ 
+ ifeq ($(CONFIG),mxe)
+ CXXFLAGS += -DYOSYS_ENABLE_TCL
+@@ -738,7 +740,7 @@ compile-only: $(OBJS) $(GENFILES) $(EXTR
+ 	@echo ""
+ 
+ $(PROGRAM_PREFIX)yosys$(EXE): $(OBJS)
+-	$(P) $(CXX) -o $(PROGRAM_PREFIX)yosys$(EXE) $(EXE_LINKFLAGS) $(LINKFLAGS) $(OBJS) $(LIBS) $(LIBS_VERIFIC)
++	$(P) $(CXX) -v -o $(PROGRAM_PREFIX)yosys$(EXE) $(EXE_LINKFLAGS) $(LINKFLAGS) $(OBJS) $(LIBS) $(LIBS_VERIFIC)
+ 
+ libyosys.so: $(filter-out kernel/driver.o,$(OBJS))
+ ifeq ($(OS), Darwin)
diff --git a/yosys-dev/patches/patch-kernel_driver.cc b/yosys-dev/patches/patch-kernel_driver.cc
new file mode 100644
index 0000000000..931cc03f64
--- /dev/null
+++ b/yosys-dev/patches/patch-kernel_driver.cc
@@ -0,0 +1,15 @@
+$NetBSD$
+
+pkgsrc cxxopts include path adjusted
+
+--- kernel/driver.cc.orig	2024-11-19 15:16:25.907765578 +0000
++++ kernel/driver.cc
+@@ -19,7 +19,7 @@
+ 
+ #include "kernel/yosys.h"
+ #include "libs/sha1/sha1.h"
+-#include "libs/cxxopts/include/cxxopts.hpp"
++#include "cxxopts.hpp"
+ #include <iostream>
+ 
+ #ifdef YOSYS_ENABLE_READLINE
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