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Sort the PLIST properly.
Module Name: pkgsrc-wip
Committed By: Lloyd Parkes <lloyd%must-have-coffee.gen.nz@localhost>
Pushed By: lloyd
Date: Tue Nov 1 09:30:56 2022 +1300
Changeset: 3ae7be30a9790f5fee88888249015437cdcb5f07
Modified Files:
icestorm-git/Makefile
yosys/Makefile
yosys/PLIST
yosys/distinfo
Added Files:
yosys/patches/patch-kernel_rtlil.cc
yosys/patches/patch-kernel_rtlil.h
Log Message:
Sort the PLIST properly.
Adjust the RTLIL::IdString::destruct_guard so that it no longer uses
a field in a static object that gets destroyed after the object is
destoyed. GCC (somewhat reasonably) appears to assume that objects
aren't accessed after they are destroyed and optimises out the old
code.
To see a diff of this commit:
https://wip.pkgsrc.org/cgi-bin/gitweb.cgi?p=pkgsrc-wip.git;a=commitdiff;h=3ae7be30a9790f5fee88888249015437cdcb5f07
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
diffstat:
icestorm-git/Makefile | 2 +-
yosys/Makefile | 3 --
yosys/PLIST | 58 ++++++++++++++++++-------------------
yosys/distinfo | 2 ++
yosys/patches/patch-kernel_rtlil.cc | 14 +++++++++
yosys/patches/patch-kernel_rtlil.h | 39 +++++++++++++++++++++++++
6 files changed, 85 insertions(+), 33 deletions(-)
diffs:
diff --git a/icestorm-git/Makefile b/icestorm-git/Makefile
index 3acdfedd1f..130b0916a2 100644
--- a/icestorm-git/Makefile
+++ b/icestorm-git/Makefile
@@ -40,6 +40,6 @@ REPLACE_FILES.usrbinenv+= icebox/icebox_maps.py
REPLACE_FILES.usrbinenv+= icebox/icebox_stat.py
REPLACE_FILES.usrbinenv+= icebox/icebox_vlog.py
-.include "../../devel/libftdi1/buildlink3.mk"
+.include "../../devel/libftdi/buildlink3.mk"
.include "../../lang/python/application.mk"
.include "../../mk/bsd.pkg.mk"
diff --git a/yosys/Makefile b/yosys/Makefile
index 183eb63bd0..55cc1d0d4a 100644
--- a/yosys/Makefile
+++ b/yosys/Makefile
@@ -61,9 +61,6 @@ SUBST_FILES.python+= tests/tools/txt2tikztiming.py
BUILDLINK_TRANSFORM= rm:-ldl
.endif
-TOOL_DEPENDS+= git-base-[0-9]*:../../devel/git-base
-TOOL_DEPENDS+= mozilla-rootcerts-openssl-[0-9]*:../../security/mozilla-rootcerts-openssl
-
do-configure:
${RUN} ${ECHO} 'CONFIG := ${YOSYS_CONFIG}' > ${WRKSRC}/Makefile.conf
diff --git a/yosys/PLIST b/yosys/PLIST
index 3c812d2e0b..29e6c2d809 100644
--- a/yosys/PLIST
+++ b/yosys/PLIST
@@ -4,6 +4,7 @@ bin/yosys-abc
bin/yosys-config
bin/yosys-filterlib
bin/yosys-smtbmc
+bin/yosys-witness
share/yosys/abc9_map.v
share/yosys/abc9_model.v
share/yosys/abc9_unmap.v
@@ -11,6 +12,8 @@ share/yosys/achronix/speedster22i/cells_map.v
share/yosys/achronix/speedster22i/cells_sim.v
share/yosys/adff2dff.v
share/yosys/anlogic/arith_map.v
+share/yosys/anlogic/brams.txt
+share/yosys/anlogic/brams_map.v
share/yosys/anlogic/cells_map.v
share/yosys/anlogic/cells_sim.v
share/yosys/anlogic/eagle_bb.v
@@ -51,7 +54,10 @@ share/yosys/gatemate/brams_init_40.vh
share/yosys/gatemate/brams_map.v
share/yosys/gatemate/cells_bb.v
share/yosys/gatemate/cells_sim.v
+share/yosys/gatemate/inv_map.v
share/yosys/gatemate/lut_map.v
+share/yosys/gatemate/lut_tree_cells.genlib
+share/yosys/gatemate/lut_tree_map.v
share/yosys/gatemate/mul_map.v
share/yosys/gatemate/mux_map.v
share/yosys/gatemate/reg_map.v
@@ -79,6 +85,8 @@ share/yosys/ice40/cells_sim.v
share/yosys/ice40/dsp_map.v
share/yosys/ice40/ff_map.v
share/yosys/ice40/latches_map.v
+share/yosys/ice40/spram.txt
+share/yosys/ice40/spram_map.v
share/yosys/include/backends/cxxrtl/cxxrtl.h
share/yosys/include/backends/cxxrtl/cxxrtl_capi.cc
share/yosys/include/backends/cxxrtl/cxxrtl_capi.h
@@ -96,6 +104,7 @@ share/yosys/include/kernel/consteval.h
share/yosys/include/kernel/constids.inc
share/yosys/include/kernel/ff.h
share/yosys/include/kernel/ffinit.h
+share/yosys/include/kernel/fstdata.h
share/yosys/include/kernel/hashlib.h
share/yosys/include/kernel/log.h
share/yosys/include/kernel/macc.h
@@ -110,6 +119,7 @@ share/yosys/include/kernel/utils.h
share/yosys/include/kernel/yosys.h
share/yosys/include/libs/ezsat/ezminisat.h
share/yosys/include/libs/ezsat/ezsat.h
+share/yosys/include/libs/fst/fstapi.h
share/yosys/include/libs/json11/json11.hpp
share/yosys/include/libs/sha1/sha1.h
share/yosys/include/passes/fsm/fsmdata.h
@@ -133,6 +143,7 @@ share/yosys/intel_alm/common/alm_map.v
share/yosys/intel_alm/common/alm_sim.v
share/yosys/intel_alm/common/arith_alm_map.v
share/yosys/intel_alm/common/bram_m10k.txt
+share/yosys/intel_alm/common/bram_m10k_map.v
share/yosys/intel_alm/common/bram_m20k.txt
share/yosys/intel_alm/common/bram_m20k_map.v
share/yosys/intel_alm/common/dff_map.v
@@ -145,8 +156,12 @@ share/yosys/intel_alm/common/mem_sim.v
share/yosys/intel_alm/common/misc_sim.v
share/yosys/intel_alm/common/quartus_rename.v
share/yosys/intel_alm/cyclonev/cells_sim.v
+share/yosys/machxo2/brams.txt
+share/yosys/machxo2/brams_map.v
share/yosys/machxo2/cells_map.v
share/yosys/machxo2/cells_sim.v
+share/yosys/machxo2/lutrams.txt
+share/yosys/machxo2/lutrams_map.v
share/yosys/mul2dsp.v
share/yosys/nexus/arith_map.v
share/yosys/nexus/brams.txt
@@ -163,6 +178,7 @@ share/yosys/nexus/lutrams_map.v
share/yosys/nexus/parse_init.vh
share/yosys/pmux2mux.v
share/yosys/python3/smtio.py
+share/yosys/python3/ywio.py
share/yosys/quicklogic/abc9_map.v
share/yosys/quicklogic/abc9_model.v
share/yosys/quicklogic/abc9_unmap.v
@@ -181,35 +197,6 @@ share/yosys/simlib.v
share/yosys/techmap.v
share/yosys/xilinx/abc9_model.v
share/yosys/xilinx/arith_map.v
-share/yosys/xilinx/cells_map.v
-share/yosys/xilinx/cells_sim.v
-share/yosys/xilinx/cells_xtra.v
-share/yosys/xilinx/ff_map.v
-share/yosys/xilinx/lut_map.v
-share/yosys/xilinx/mux_map.v
-share/yosys/xilinx/xc3s_mult_map.v
-share/yosys/xilinx/xc3sda_dsp_map.v
-share/yosys/xilinx/xc4v_dsp_map.v
-share/yosys/xilinx/xc5v_dsp_map.v
-share/yosys/xilinx/xc6s_dsp_map.v
-share/yosys/xilinx/xc7_dsp_map.v
-share/yosys/xilinx/xcu_dsp_map.v
-bin/yosys-witness
-share/yosys/anlogic/brams.txt
-share/yosys/anlogic/brams_map.v
-share/yosys/gatemate/inv_map.v
-share/yosys/gatemate/lut_tree_cells.genlib
-share/yosys/gatemate/lut_tree_map.v
-share/yosys/ice40/spram.txt
-share/yosys/ice40/spram_map.v
-share/yosys/include/kernel/fstdata.h
-share/yosys/include/libs/fst/fstapi.h
-share/yosys/intel_alm/common/bram_m10k_map.v
-share/yosys/machxo2/brams.txt
-share/yosys/machxo2/brams_map.v
-share/yosys/machxo2/lutrams.txt
-share/yosys/machxo2/lutrams_map.v
-share/yosys/python3/ywio.py
share/yosys/xilinx/brams_defs.vh
share/yosys/xilinx/brams_xc2v.txt
share/yosys/xilinx/brams_xc2v_map.v
@@ -222,10 +209,23 @@ share/yosys/xilinx/brams_xc6v_map.v
share/yosys/xilinx/brams_xcu_map.v
share/yosys/xilinx/brams_xcv.txt
share/yosys/xilinx/brams_xcv_map.v
+share/yosys/xilinx/cells_map.v
+share/yosys/xilinx/cells_sim.v
+share/yosys/xilinx/cells_xtra.v
+share/yosys/xilinx/ff_map.v
+share/yosys/xilinx/lut_map.v
share/yosys/xilinx/lutrams_xc5v.txt
share/yosys/xilinx/lutrams_xc5v_map.v
share/yosys/xilinx/lutrams_xcu.txt
share/yosys/xilinx/lutrams_xcv.txt
share/yosys/xilinx/lutrams_xcv_map.v
+share/yosys/xilinx/mux_map.v
share/yosys/xilinx/urams.txt
share/yosys/xilinx/urams_map.v
+share/yosys/xilinx/xc3s_mult_map.v
+share/yosys/xilinx/xc3sda_dsp_map.v
+share/yosys/xilinx/xc4v_dsp_map.v
+share/yosys/xilinx/xc5v_dsp_map.v
+share/yosys/xilinx/xc6s_dsp_map.v
+share/yosys/xilinx/xc7_dsp_map.v
+share/yosys/xilinx/xcu_dsp_map.v
diff --git a/yosys/distinfo b/yosys/distinfo
index 69e402c814..546fe26c5a 100644
--- a/yosys/distinfo
+++ b/yosys/distinfo
@@ -3,6 +3,8 @@ $NetBSD$
BLAKE2s (yosys-0.22.tar.gz) = 4983725a68e89f2e5dbc341beb5deba28906c6ca84ecfe8deae1dba1fbb69ff7
SHA512 (yosys-0.22.tar.gz) = d546196a6875b0ecaaab44437b5691f08890576eed357ac99dce233a0afd352a56742f5286da406e4e5513be32db99811fc6caa7a7a605a94af3903670fbf616
Size (yosys-0.22.tar.gz) = 2362180 bytes
+SHA1 (patch-kernel_rtlil.cc) = 9e85969577560c67dd40d2fa63702ca103511a4e
+SHA1 (patch-kernel_rtlil.h) = 6a50b94a8f053df1816739f4a87a9933cc1789ac
SHA1 (patch-kernel_yosys.cc) = 81e504f0a61baa47eca7cec021ae60d8ed432e3b
SHA1 (patch-libs_fst_fstapi.cc) = 3be81ba51fc67b4578f956513dc5e3c531c7240d
SHA1 (patch-tests_sim_run-test.sh) = 9f8149dcb024ab93f723ed0f85dd88a58168bf62
diff --git a/yosys/patches/patch-kernel_rtlil.cc b/yosys/patches/patch-kernel_rtlil.cc
new file mode 100644
index 0000000000..82954cf8bb
--- /dev/null
+++ b/yosys/patches/patch-kernel_rtlil.cc
@@ -0,0 +1,14 @@
+$NetBSD$
+
+Add a destructor guard that can be accessed after the destructors are run.
+
+--- kernel/rtlil.cc.orig 2022-10-05 09:30:38.000000000 +0000
++++ kernel/rtlil.cc
+@@ -30,6 +30,7 @@
+
+ YOSYS_NAMESPACE_BEGIN
+
++bool RTLIL::IdString::destruct_guard_ok;
+ RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
+ std::vector<char*> RTLIL::IdString::global_id_storage_;
+ dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
diff --git a/yosys/patches/patch-kernel_rtlil.h b/yosys/patches/patch-kernel_rtlil.h
new file mode 100644
index 0000000000..eae8f4fed9
--- /dev/null
+++ b/yosys/patches/patch-kernel_rtlil.h
@@ -0,0 +1,39 @@
+$NetBSD$
+
+Move the ok flag out of the destruct_guard_t so that GCC won't optimise
+~destruct_guard_t() into a NO-OP.
+
+--- kernel/rtlil.h.orig 2022-10-05 09:30:38.000000000 +0000
++++ kernel/rtlil.h
+@@ -85,10 +85,10 @@ namespace RTLIL
+
+ // the global id string cache
+
++ bool destruct_guard_ok; // POD, will be initialized to zero
+ static struct destruct_guard_t {
+- bool ok; // POD, will be initialized to zero
+- destruct_guard_t() { ok = true; }
+- ~destruct_guard_t() { ok = false; }
++ destruct_guard_t() { destruct_guard_ok = true; }
++ ~destruct_guard_t() { destruct_guard_ok = false; }
+ } destruct_guard;
+
+ static std::vector<char*> global_id_storage_;
+@@ -147,7 +147,7 @@ namespace RTLIL
+
+ static int get_reference(const char *p)
+ {
+- log_assert(destruct_guard.ok);
++ log_assert(destruct_guard_ok);
+
+ if (!p[0])
+ return 0;
+@@ -225,7 +225,7 @@ namespace RTLIL
+ {
+ // put_reference() may be called from destructors after the destructor of
+ // global_refcount_storage_ has been run. in this case we simply do nothing.
+- if (!destruct_guard.ok || !idx)
++ if (!destruct_guard_ok || !idx)
+ return;
+
+ #ifdef YOSYS_XTRACE_GET_PUT
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