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lldb-netbsd: Fix reading arm64 registers from core files
Module Name: pkgsrc-wip
Committed By: Kamil Rytarowski <n54%gmx.com@localhost>
Pushed By: kamil
Date: Tue Apr 17 16:55:45 2018 +0200
Changeset: e617525a176a743ee9857039492109ef18360188
Modified Files:
lldb-netbsd/distinfo
lldb-netbsd/patches/patch-source_Plugins_Process_elf-core_ProcessElfCore.cpp
Added Files:
lldb-netbsd/patches/patch-source_Plugins_Process_elf-core_RegisterContextPOSIXCore__arm64.cpp
Log Message:
lldb-netbsd: Fix reading arm64 registers from core files
Add a local hack to transform 128 registers into 64 ones.
This seems to work:
$ LD_LIBRARY_PATH=/usr/pkg/lib PATH=/public/llvm-build/bin/:$PATH lldb -c ./a.out.core ./a.out
(lldb) target create "./a.out" --core "./a.out.core"
Core file '/public/core-arm64/./a.out.core' (aarch64) was loaded.
(lldb) bt
* thread #1, stop reason = signal SIGSEGV
* frame #0: 0x0000000200100990 a.out`main(argc=1, argv=0x0000ffffffb97a88) at test.c:27
frame #1: 0x0000000200100834 a.out`___start + 320
(lldb) register read -a
General Purpose Registers:
x0 = 0x0000000000000013
x1 = 0x0000000000000000
x2 = 0x0000ffffffb97a98
x3 = 0x0000000000000000
x4 = 0x0000fffff953e1e0
x5 = 0x0000000000000000
x6 = 0x0000ffffffb979a0
x7 = 0x0000000000000000
x8 = 0x0000000000000000
x9 = 0x0000f747d5bb0000
x10 = 0x00000002001004f2
x11 = 0x0000000000000000
x12 = 0x000000000000000c
x13 = 0x000003dd1f5750c1
x14 = 0x0000000000000010
x15 = 0x0000f747d5d42060
x16 = 0x0000f747d5d24ba8
x17 = 0x0000f747d5bf2d40
x18 = 0x000000000016d9b8
x19 = 0x0000ffffffb98fe0
x20 = 0x0000000200110e68 a.out`environ
x21 = 0x0000000200110bf0 a.out`__JCR_LIST__
x22 = 0x0000000200110bf0 a.out`__JCR_LIST__
x23 = 0x0000000000000000
x24 = 0x0000ffffffb98fe0
x25 = 0x0000fffff9520000
x26 = 0x0000000000000000
x27 = 0x0000000000000000
x28 = 0x0000000000000000
fp = 0x0000ffffffb97a40
lr = 0x000000020010097c a.out`main + 32 at test.c:27
sp = 0x0000ffffffb97a30
pc = 0x0000000200100990 a.out`main + 52 at test.c:27
cpsr = 0x60000000
w0 = 0x00000013
w1 = 0x00000000
w2 = 0xffb97a98
w3 = 0x00000000
w4 = 0xf953e1e0
w5 = 0x00000000
w6 = 0xffb979a0
w7 = 0x00000000
w8 = 0x00000000
w9 = 0xd5bb0000
w10 = 0x001004f2
w11 = 0x00000000
w12 = 0x0000000c
w13 = 0x1f5750c1
w14 = 0x00000010
w15 = 0xd5d42060
w16 = 0xd5d24ba8
w17 = 0xd5bf2d40
w18 = 0x0016d9b8
w19 = 0xffb98fe0
w20 = 0x00110e68
w21 = 0x00110bf0
w22 = 0x00110bf0
w23 = 0x00000000
w24 = 0xffb98fe0
w25 = 0xf9520000
w26 = 0x00000000
w27 = 0x00000000
w28 = 0x00000000
Floating Point Registers:
s0 = -2.91628e+13
d0 = 1.34330471992722e-309
96 registers were unavailable.
(lldb)
For a clean room implementation we need to support APInt (Arbitrary
Precision Integers) to handle 128bit regiters. Upstream will request
new tests for this.. but there are greater problems with the NetBSD
support as of now.
Sponsored by <The NetBSD Foundation>
To see a diff of this commit:
https://wip.pkgsrc.org/cgi-bin/gitweb.cgi?p=pkgsrc-wip.git;a=commitdiff;h=e617525a176a743ee9857039492109ef18360188
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
diffstat:
lldb-netbsd/distinfo | 3 ++-
...ource_Plugins_Process_elf-core_ProcessElfCore.cpp | 16 +++-------------
...cess_elf-core_RegisterContextPOSIXCore__arm64.cpp | 20 ++++++++++++++++++++
3 files changed, 25 insertions(+), 14 deletions(-)
diffs:
diff --git a/lldb-netbsd/distinfo b/lldb-netbsd/distinfo
index faad2ccba9..08a2474c37 100644
--- a/lldb-netbsd/distinfo
+++ b/lldb-netbsd/distinfo
@@ -13,6 +13,7 @@ SHA1 (llvm-3.6.2.src.tar.xz) = 7a00257eb2bc9431e4c77c3a36b033072c54bc7e
RMD160 (llvm-3.6.2.src.tar.xz) = 521cbc5fe2925ea3c6e90c7a31f752a04045c972
Size (llvm-3.6.2.src.tar.xz) = 12802380 bytes
SHA1 (patch-source_Plugins_ObjectFile_ELF_ObjectFileELF.cpp) = 6da890620fb393f202d2acc6402b96dbb0b82928
-SHA1 (patch-source_Plugins_Process_elf-core_ProcessElfCore.cpp) = 90f9ce4bdbdfbfab2090b7296a00c66dacd126d6
+SHA1 (patch-source_Plugins_Process_elf-core_ProcessElfCore.cpp) = 048ad92f569745ab363c8d19a8081812abc94ae6
+SHA1 (patch-source_Plugins_Process_elf-core_RegisterContextPOSIXCore__arm64.cpp) = e5d14323468130da799f4f44852ccddf6cbc62ee
SHA1 (patch-source_Plugins_Process_elf-core_RegisterUtilities.h) = e1f3d5eb7b050e92f6d1d57ea31266eb3a8720ad
SHA1 (patch-source_Plugins_Process_elf-core_ThreadElfCore.cpp) = 9ef247cde8681d060263ccd25d7128f7c7d38e30
diff --git a/lldb-netbsd/patches/patch-source_Plugins_Process_elf-core_ProcessElfCore.cpp b/lldb-netbsd/patches/patch-source_Plugins_Process_elf-core_ProcessElfCore.cpp
index 28e9921a54..c11a67fa6f 100644
--- a/lldb-netbsd/patches/patch-source_Plugins_Process_elf-core_ProcessElfCore.cpp
+++ b/lldb-netbsd/patches/patch-source_Plugins_Process_elf-core_ProcessElfCore.cpp
@@ -52,7 +52,7 @@ $NetBSD$
}
static void ParseOpenBSDProcInfo(ThreadData &thread_data,
-@@ -550,35 +577,113 @@ llvm::Error ProcessElfCore::parseFreeBSD
+@@ -550,35 +577,103 @@ llvm::Error ProcessElfCore::parseFreeBSD
llvm::Error ProcessElfCore::parseNetBSDNotes(llvm::ArrayRef<CoreNote> notes) {
ThreadData thread_data;
@@ -112,12 +112,7 @@ $NetBSD$
+ m_thread_data.back().gpregset = note.data;
+ m_thread_data.back().tid = tid;
+ } else if (note.info.n_type == NETBSD::AMD64::NT_FPREGS) {
-+#if notyet
-+ if (m_thread_data.empty() || tid != m_thread_data.back().tid)
-+ return Status("Error parsing NetBSD core(5) notes: Unexpected order "
-+ "of NOTEs PT_GETFPREG before PT_GETREG").ToError();
-+ m_thread_data.back().fpregset = note.data;
-+#endif
++ m_thread_data.back().notes.push_back(note);
+ } else {
+ return Status(
+ "Error parsing NetBSD core(5) notes: Unsupported AMD64 NOTE").ToError();
@@ -131,12 +126,7 @@ $NetBSD$
+ m_thread_data.back().gpregset = note.data;
+ m_thread_data.back().tid = tid;
+ } else if (note.info.n_type == NETBSD::AARCH64::NT_FPREGS) {
-+#if notyet
-+ if (m_thread_data.empty() || tid != m_thread_data.back().tid)
-+ return Status("Error parsing NetBSD core(5) notes: Unexpected order "
-+ "of NOTEs PT_GETFPREG before PT_GETREG").ToError();
-+ m_thread_data.back().fpregset = note.data;
-+#endif
++ m_thread_data.back().notes.push_back(note); // We need to implement an extractor of 128bit integers
+ } else {
+ return Status(
+ "Error parsing NetBSD core(5) notes: Unsupported EVBARM NOTE").ToError();
diff --git a/lldb-netbsd/patches/patch-source_Plugins_Process_elf-core_RegisterContextPOSIXCore__arm64.cpp b/lldb-netbsd/patches/patch-source_Plugins_Process_elf-core_RegisterContextPOSIXCore__arm64.cpp
new file mode 100644
index 0000000000..117ad5bfd0
--- /dev/null
+++ b/lldb-netbsd/patches/patch-source_Plugins_Process_elf-core_RegisterContextPOSIXCore__arm64.cpp
@@ -0,0 +1,20 @@
+$NetBSD$
+
+--- source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp.orig 2018-02-02 18:39:12.000000000 +0000
++++ source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
+@@ -43,7 +43,14 @@ bool RegisterContextCorePOSIX_arm64::Wri
+ bool RegisterContextCorePOSIX_arm64::ReadRegister(const RegisterInfo *reg_info,
+ RegisterValue &value) {
+ lldb::offset_t offset = reg_info->byte_offset;
+- uint64_t v = m_gpr.GetMaxU64(&offset, reg_info->byte_size);
++ uint64_t v;
++
++ if (reg_info->byte_size == 16) {
++ v = m_gpr.GetMaxU64(&offset, 8);
++ v = m_gpr.GetMaxU64(&offset, 8);
++ } else {
++ v = m_gpr.GetMaxU64(&offset, reg_info->byte_size);
++ }
+ if (offset == reg_info->byte_offset + reg_info->byte_size) {
+ value = v;
+ return true;
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