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CVS commit: pkgsrc/emulators/qemu51
Module Name: pkgsrc
Committed By: ryoon
Date: Sat Feb 20 22:55:19 UTC 2021
Added Files:
pkgsrc/emulators/qemu51: DESCR Makefile PLIST distinfo options.mk
pkgsrc/emulators/qemu51/files: Makefile.multinode-NetBSD
hw-mips-mipssim_virtio.c
pkgsrc/emulators/qemu51/patches: patch-Makefile
patch-accel_stubs_Makefile.objs patch-accel_stubs_nvmm-stub.c
patch-backends_tpm_tpm__ioctl.h patch-capstone_Makefile
patch-configure patch-contrib_ivshmem-client_ivshmem-client.c
patch-contrib_ivshmem-server_ivshmem-server.c
patch-default-configs-mips-softmmu-common.mak patch-hw-mips-Kconfig
patch-hw-mips-Makefiles.objs patch-hw-mips-mipssim.c
patch-hw_alpha_alpha_sys.h patch-hw_alpha_dp264.c
patch-hw_alpha_typhoon.c patch-hw_core_uboot__image.h
patch-hw_display_omap__dss.c patch-hw_display_tcx.c
patch-hw_net_etraxfs__eth.c patch-hw_net_xilinx__axienet.c
patch-hw_pci-host_sabre.c patch-hw_rtc_mc146818rtc.c
patch-hw_scsi_scsi-disk.c patch-hw_usb_dev-mtp.c
patch-include_sysemu_hw__accel.h patch-include_sysemu_kvm.h
patch-include_sysemu_nvmm.h patch-net_tap-solaris.c
patch-qemu-options.hx patch-roms_qemu-palcode_hwrpb.h
patch-roms_qemu-palcode_init.c patch-roms_qemu-palcode_memcpy.c
patch-roms_qemu-palcode_memset.c patch-roms_qemu-palcode_pal.S
patch-roms_qemu-palcode_pci.c patch-roms_qemu-palcode_pci.h
patch-roms_qemu-palcode_printf.c patch-roms_qemu-palcode_protos.h
patch-roms_qemu-palcode_sys-clipper.h
patch-roms_qemu-palcode_vgaio.c patch-roms_u-boot-sam460ex_Makefile
patch-roms_u-boot_tools_imx8m__image.sh patch-softmmu_cpus.c
patch-target_i386_Makefile.objs patch-target_i386_helper.c
patch-target_i386_kvm-stub.c patch-target_i386_nvmm-all.c
patch-target_sparc_translate.c
Log Message:
emulators/qemu51: import qemu-5.1.0nb13
QEMU is a FAST! processor emulator using dynamic translation to achieve
good emulation speed, QEMU has two operating modes:
* Full system emulation. In this mode, QEMU emulates a full system
(for example a PC), including a processor and various peripherals.
It can be used to launch different Operating Systems without rebooting
the PC or to debug system code.
* User mode emulation (Linux host only). In this mode, QEMU can launch
Linux processes compiled for one CPU on another CPU. It can be used
to launch the Wine Windows API emulator or to ease cross-compilation
and cross-debugging.
This package contains Qemu 5.1.0 with NetBSD NVMM support.
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 pkgsrc/emulators/qemu51/DESCR \
pkgsrc/emulators/qemu51/Makefile pkgsrc/emulators/qemu51/PLIST \
pkgsrc/emulators/qemu51/distinfo pkgsrc/emulators/qemu51/options.mk
cvs rdiff -u -r0 -r1.1 \
pkgsrc/emulators/qemu51/files/Makefile.multinode-NetBSD \
pkgsrc/emulators/qemu51/files/hw-mips-mipssim_virtio.c
cvs rdiff -u -r0 -r1.1 pkgsrc/emulators/qemu51/patches/patch-Makefile \
pkgsrc/emulators/qemu51/patches/patch-accel_stubs_Makefile.objs \
pkgsrc/emulators/qemu51/patches/patch-accel_stubs_nvmm-stub.c \
pkgsrc/emulators/qemu51/patches/patch-backends_tpm_tpm__ioctl.h \
pkgsrc/emulators/qemu51/patches/patch-capstone_Makefile \
pkgsrc/emulators/qemu51/patches/patch-configure \
pkgsrc/emulators/qemu51/patches/patch-contrib_ivshmem-client_ivshmem-client.c \
pkgsrc/emulators/qemu51/patches/patch-contrib_ivshmem-server_ivshmem-server.c \
pkgsrc/emulators/qemu51/patches/patch-default-configs-mips-softmmu-common.mak \
pkgsrc/emulators/qemu51/patches/patch-hw-mips-Kconfig \
pkgsrc/emulators/qemu51/patches/patch-hw-mips-Makefiles.objs \
pkgsrc/emulators/qemu51/patches/patch-hw-mips-mipssim.c \
pkgsrc/emulators/qemu51/patches/patch-hw_alpha_alpha_sys.h \
pkgsrc/emulators/qemu51/patches/patch-hw_alpha_dp264.c \
pkgsrc/emulators/qemu51/patches/patch-hw_alpha_typhoon.c \
pkgsrc/emulators/qemu51/patches/patch-hw_core_uboot__image.h \
pkgsrc/emulators/qemu51/patches/patch-hw_display_omap__dss.c \
pkgsrc/emulators/qemu51/patches/patch-hw_display_tcx.c \
pkgsrc/emulators/qemu51/patches/patch-hw_net_etraxfs__eth.c \
pkgsrc/emulators/qemu51/patches/patch-hw_net_xilinx__axienet.c \
pkgsrc/emulators/qemu51/patches/patch-hw_pci-host_sabre.c \
pkgsrc/emulators/qemu51/patches/patch-hw_rtc_mc146818rtc.c \
pkgsrc/emulators/qemu51/patches/patch-hw_scsi_scsi-disk.c \
pkgsrc/emulators/qemu51/patches/patch-hw_usb_dev-mtp.c \
pkgsrc/emulators/qemu51/patches/patch-include_sysemu_hw__accel.h \
pkgsrc/emulators/qemu51/patches/patch-include_sysemu_kvm.h \
pkgsrc/emulators/qemu51/patches/patch-include_sysemu_nvmm.h \
pkgsrc/emulators/qemu51/patches/patch-net_tap-solaris.c \
pkgsrc/emulators/qemu51/patches/patch-qemu-options.hx \
pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_hwrpb.h \
pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_init.c \
pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_memcpy.c \
pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_memset.c \
pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_pal.S \
pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_pci.c \
pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_pci.h \
pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_printf.c \
pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_protos.h \
pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_sys-clipper.h \
pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_vgaio.c \
pkgsrc/emulators/qemu51/patches/patch-roms_u-boot-sam460ex_Makefile \
pkgsrc/emulators/qemu51/patches/patch-roms_u-boot_tools_imx8m__image.sh \
pkgsrc/emulators/qemu51/patches/patch-softmmu_cpus.c \
pkgsrc/emulators/qemu51/patches/patch-target_i386_Makefile.objs \
pkgsrc/emulators/qemu51/patches/patch-target_i386_helper.c \
pkgsrc/emulators/qemu51/patches/patch-target_i386_kvm-stub.c \
pkgsrc/emulators/qemu51/patches/patch-target_i386_nvmm-all.c \
pkgsrc/emulators/qemu51/patches/patch-target_sparc_translate.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Added files:
Index: pkgsrc/emulators/qemu51/DESCR
diff -u /dev/null pkgsrc/emulators/qemu51/DESCR:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/DESCR Sat Feb 20 22:55:19 2021
@@ -0,0 +1,13 @@
+QEMU is a FAST! processor emulator using dynamic translation to achieve
+good emulation speed, QEMU has two operating modes:
+
+ * Full system emulation. In this mode, QEMU emulates a full system
+ (for example a PC), including a processor and various peripherals.
+ It can be used to launch different Operating Systems without rebooting
+ the PC or to debug system code.
+ * User mode emulation (Linux host only). In this mode, QEMU can launch
+ Linux processes compiled for one CPU on another CPU. It can be used
+ to launch the Wine Windows API emulator or to ease cross-compilation
+ and cross-debugging.
+
+This package contains Qemu 5.1.0 with NetBSD NVMM support.
Index: pkgsrc/emulators/qemu51/Makefile
diff -u /dev/null pkgsrc/emulators/qemu51/Makefile:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/Makefile Sat Feb 20 22:55:19 2021
@@ -0,0 +1,182 @@
+# $NetBSD: Makefile,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+DISTNAME= qemu-5.1.0
+PKGREVISION= 13
+CATEGORIES= emulators
+MASTER_SITES= https://download.qemu.org/
+EXTRACT_SUFX= .tar.xz
+
+MAINTAINER= pkgsrc-users%NetBSD.org@localhost
+HOMEPAGE= http://www.qemu-project.org/
+COMMENT= CPU emulator using dynamic translation
+LICENSE= gnu-gpl-v2 AND gnu-lgpl-v2.1 AND mit AND modified-bsd
+
+USE_CURSES= resize_term wide
+USE_LANGUAGES+= c c++
+USE_TOOLS+= bison flex gmake makeinfo perl:build pod2man pkg-config
+FAKE_NCURSES= yes
+UNLIMIT_RESOURCES= datasize
+HAS_CONFIGURE= yes
+
+GMAKE_REQD= 4.1 # needed for docs
+
+PYTHON_VERSIONED_DEPENDENCIES= sphinx:tool
+
+SUBST_CLASSES+= sphinx-build
+SUBST_STAGE.sphinx-build= pre-configure
+SUBST_MESSAGE.sphinx-build= Fix hardcoded sphinx-build
+SUBST_FILES.sphinx-build+= configure
+SUBST_FILES.sphinx-build+= roms/skiboot/doc/Makefile
+SUBST_FILES.sphinx-build+= roms/u-boot/Documentation/Makefile
+SUBST_SED.sphinx-build+= -e 's/sphinx-build/sphinx-build-${PYVERSSUFFIX}/g'
+
+.include "options.mk"
+
+.include "../../mk/bsd.prefs.mk"
+
+DISTFILES= ${DEFAULT_DISTFILES}
+DISTFILES+= palcode-clipper
+SITES.palcode-clipper= http://ftp.netbsd.org/pub/NetBSD/arch/alpha/qemu/
+
+CONFIGURE_ARGS+= --prefix=${PREFIX}
+CONFIGURE_ARGS+= --interp-prefix=${PREFIX}/share/qemu
+CONFIGURE_ARGS+= --sysconfdir=${PKG_SYSCONFDIR}
+CONFIGURE_ARGS+= --python=${PYTHONBIN}
+CONFIGURE_ARGS+= --smbd=${PREFIX}/sbin/smbd
+CONFIGURE_ARGS+= --mandir=${PREFIX}/${PKGMANDIR}
+CONFIGURE_ARGS+= --enable-curses
+CONFIGURE_ARGS+= --enable-docs
+CONFIGURE_ARGS+= --enable-jemalloc
+CONFIGURE_ENV+= mansuffix=/${PKGMANDIR}
+
+.if defined(PKGSRC_USE_SSP)
+# do not add flags to everything
+PKGSRC_USE_SSP= no
+CONFIGURE_ARGS+= --enable-stack-protector
+.endif
+
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-aarch64
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-alpha
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-arm
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-cris
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-hppa
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-i386
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-lm32
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-m68k
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-microblaze
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-microblazeel
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-mips
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-mips64
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-mips64el
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-mipsel
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-moxie
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-nios2
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-or1k
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-ppc
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-ppc64
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-riscv32
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-riscv64
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-s390x
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-sh4
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-sh4eb
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-sparc
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-sparc64
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-tricore
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-unicore32
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-x86_64
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-xtensa
+NOT_PAX_MPROTECT_SAFE+= bin/qemu-system-xtensaeb
+
+PKG_SYSCONFSUBDIR= qemu
+
+REPLACE_PERL+= scripts/texi2pod.pl
+
+INSTALLATION_DIRS= ${PKGMANDIR}/man1 share/doc/qemu
+
+UE_ARCHS+= aarch64 aarch64_be
+UE_ARCHS+= alpha arm armeb cris
+UE_ARCHS+= hppa
+UE_ARCHS+= i386
+UE_ARCHS+= m68k microblaze microblazeel
+UE_ARCHS+= mips mips64 mips64el mipsel mipsn32 mipsn32el
+UE_ARCHS+= nios2
+UE_ARCHS+= or1k ppc ppc64 ppc64le ppc64abi32
+UE_ARCHS+= riscv32 riscv64
+UE_ARCHS+= s390x sh4 sh4eb sparc sparc32plus sparc64
+UE_ARCHS+= tilegx
+UE_ARCHS+= x86_64 xtensa xtensaeb
+
+.if ${OPSYS} == "NetBSD"
+PLIST.nbd= yes
+. if !exists(/usr/include/machine/trap.h)
+CONFIGURE_ARGS+= --disable-bsd-user
+. else
+USER_EMUL= i386 x86_64 sparc sparc64
+. endif
+.elif !empty(OPSYS:M*BSD) || ${OPSYS} == "DragonFly"
+USER_EMUL= i386 x86_64 sparc sparc64
+PLIST.nbd= yes
+.elif ${OPSYS} == "Darwin"
+USER_EMUL=
+CONFIGURE_ARGS+= --disable-bsd-user
+PLIST.nbd= yes
+.elif ${OPSYS} == "Linux"
+USER_EMUL= ${UE_ARCHS}
+PLIST.bridge-helper= yes
+PLIST.nbd= yes
+PLIST.ivshmem= yes
+PLIST.pr-helper= yes
+.elif !empty(MACHINE_PLATFORM:MSunOS-5.11-*)
+PLIST.ivshmem= yes
+PLIST.nbd= yes
+CONFIGURE_ARGS+= --disable-coroutine-pool
+.endif
+
+PLIST_VARS+= ${UE_ARCHS} bridge-helper ivshmem keymap nbd pr-helper
+.for pvar in ${USER_EMUL}
+PLIST.${pvar}= yes
+.endfor
+
+# different versions of Sphinx generate different static files
+PLIST_SRC= PLIST ${WRKDIR}/PLIST.STATIC
+
+TEST_TARGET= check
+
+post-extract:
+ cp ${WRKDIR}/palcode-clipper ${WRKSRC}/pc-bios/palcode-clipper
+ cp ${FILESDIR}/hw-mips-mipssim_virtio.c ${WRKSRC}/hw/mips/mipssim_virtio.c
+
+# Some dependencies aren't correct and this tries to be re-made on install,
+# failing due to configure bugs.
+post-build:
+ ${TOUCH} ${WRKSRC}/config-host.mak
+
+post-install:
+ ${INSTALL_DATA} ${FILESDIR}/Makefile.multinode-NetBSD \
+ ${DESTDIR}${PREFIX}/share/doc/qemu/
+ ${RM} -f ${DESTDIR}${PREFIX}/share/doc/qemu/interop/.buildinfo
+ ${RM} -f ${DESTDIR}${PREFIX}/share/doc/qemu/specs/.buildinfo
+ ${RM} -f ${WRKDIR}/PLIST.STATIC
+ cd ${DESTDIR}${PREFIX} && \
+ ${FIND} share/doc/qemu -path '*/_static/*' -type f -print > ${WRKDIR}/PLIST.STATIC
+
+# On Darwin, qemu uses CoreAudio
+.if ${OPSYS} != "Darwin"
+.include "../../mk/oss.buildlink3.mk"
+.endif
+.include "../../archivers/lzo/buildlink3.mk"
+.include "../../devel/glib2/buildlink3.mk"
+.include "../../devel/jemalloc/buildlink3.mk"
+.include "../../devel/snappy/buildlink3.mk"
+.include "../../devel/zlib/buildlink3.mk"
+.include "../../graphics/hicolor-icon-theme/buildlink3.mk"
+.include "../../graphics/png/buildlink3.mk"
+.include "../../lang/python/extension.mk"
+.include "../../lang/python/versioned_dependencies.mk"
+.include "../../security/libgcrypt/buildlink3.mk"
+.include "../../www/curl/buildlink3.mk"
+.include "../../x11/pixman/buildlink3.mk"
+.include "../../mk/curses.buildlink3.mk"
+.include "../../mk/jpeg.buildlink3.mk"
+.include "../../mk/pthread.buildlink3.mk"
+.include "../../mk/bsd.pkg.mk"
Index: pkgsrc/emulators/qemu51/PLIST
diff -u /dev/null pkgsrc/emulators/qemu51/PLIST:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/PLIST Sat Feb 20 22:55:19 2021
@@ -0,0 +1,403 @@
+@comment $NetBSD: PLIST,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+bin/elf2dmp
+${PLIST.ivshmem}bin/ivshmem-client
+${PLIST.ivshmem}bin/ivshmem-server
+${PLIST.aarch64}bin/qemu-aarch64
+${PLIST.aarch64_be}bin/qemu-aarch64_be
+${PLIST.alpha}bin/qemu-alpha
+${PLIST.arm}bin/qemu-arm
+${PLIST.armeb}bin/qemu-armeb
+${PLIST.cris}bin/qemu-cris
+bin/qemu-edid
+bin/qemu-ga
+${PLIST.hppa}bin/qemu-hppa
+${PLIST.i386}bin/qemu-i386
+bin/qemu-img
+bin/qemu-io
+${PLIST.keymap}bin/qemu-keymap
+${PLIST.m68k}bin/qemu-m68k
+${PLIST.microblaze}bin/qemu-microblaze
+${PLIST.microblazeel}bin/qemu-microblazeel
+${PLIST.mips}bin/qemu-mips
+${PLIST.mips64}bin/qemu-mips64
+${PLIST.mips64el}bin/qemu-mips64el
+${PLIST.mipsel}bin/qemu-mipsel
+${PLIST.mipsn32}bin/qemu-mipsn32
+${PLIST.mipsn32el}bin/qemu-mipsn32el
+${PLIST.nbd}bin/qemu-nbd
+${PLIST.nios2}bin/qemu-nios2
+${PLIST.or1k}bin/qemu-or1k
+${PLIST.ppc}bin/qemu-ppc
+${PLIST.ppc64}bin/qemu-ppc64
+${PLIST.ppc64abi32}bin/qemu-ppc64abi32
+${PLIST.ppc64le}bin/qemu-ppc64le
+${PLIST.riscv32}bin/qemu-riscv32
+${PLIST.riscv64}bin/qemu-riscv64
+${PLIST.s390x}bin/qemu-s390x
+${PLIST.sh4}bin/qemu-sh4
+${PLIST.sh4eb}bin/qemu-sh4eb
+${PLIST.sparc}bin/qemu-sparc
+${PLIST.sparc32plus}bin/qemu-sparc32plus
+${PLIST.sparc64}bin/qemu-sparc64
+bin/qemu-storage-daemon
+bin/qemu-system-aarch64
+bin/qemu-system-alpha
+bin/qemu-system-arm
+bin/qemu-system-avr
+bin/qemu-system-cris
+bin/qemu-system-hppa
+bin/qemu-system-i386
+bin/qemu-system-lm32
+bin/qemu-system-m68k
+bin/qemu-system-microblaze
+bin/qemu-system-microblazeel
+bin/qemu-system-mips
+bin/qemu-system-mips64
+bin/qemu-system-mips64el
+bin/qemu-system-mipsel
+bin/qemu-system-moxie
+bin/qemu-system-nios2
+bin/qemu-system-or1k
+bin/qemu-system-ppc
+bin/qemu-system-ppc64
+bin/qemu-system-riscv32
+bin/qemu-system-riscv64
+bin/qemu-system-rx
+bin/qemu-system-s390x
+bin/qemu-system-sh4
+bin/qemu-system-sh4eb
+bin/qemu-system-sparc
+bin/qemu-system-sparc64
+bin/qemu-system-tricore
+bin/qemu-system-unicore32
+bin/qemu-system-x86_64
+bin/qemu-system-xtensa
+bin/qemu-system-xtensaeb
+${PLIST.tilegx}bin/qemu-tilegx
+${PLIST.x86_64}bin/qemu-x86_64
+${PLIST.xtensa}bin/qemu-xtensa
+${PLIST.xtensaeb}bin/qemu-xtensaeb
+${PLIST.bridge-helper}libexec/qemu-bridge-helper
+${PLIST.pr-helper}libexec/qemu-pr-helper
+${PLIST.virtfs-proxy-helper}libexec/virtfs-proxy-helper
+man/man1/qemu-img.1
+man/man1/qemu.1
+${PLIST.virtfs-proxy-helper}man/man1/virtfs-proxy-helper.1
+man/man7/qemu-block-drivers.7
+man/man7/qemu-cpu-models.7
+man/man7/qemu-ga-ref.7
+man/man7/qemu-qmp-ref.7
+man/man8/qemu-ga.8
+man/man8/qemu-nbd.8
+share/applications/qemu.desktop
+share/doc/qemu/Makefile.multinode-NetBSD
+share/doc/qemu/index.html
+share/doc/qemu/interop/_static/alabaster.css
+share/doc/qemu/interop/_static/basic.css
+share/doc/qemu/interop/_static/custom.css
+share/doc/qemu/interop/_static/doctools.js
+share/doc/qemu/interop/_static/documentation_options.js
+share/doc/qemu/interop/_static/file.png
+share/doc/qemu/interop/_static/jquery-3.4.1.js
+share/doc/qemu/interop/_static/jquery.js
+share/doc/qemu/interop/_static/language_data.js
+share/doc/qemu/interop/_static/minus.png
+share/doc/qemu/interop/_static/plus.png
+share/doc/qemu/interop/_static/pygments.css
+share/doc/qemu/interop/_static/searchtools.js
+share/doc/qemu/interop/_static/underscore-1.3.1.js
+share/doc/qemu/interop/_static/underscore.js
+share/doc/qemu/interop/bitmaps.html
+share/doc/qemu/interop/dbus-vmstate.html
+share/doc/qemu/interop/dbus.html
+share/doc/qemu/interop/genindex.html
+share/doc/qemu/interop/index.html
+share/doc/qemu/interop/live-block-operations.html
+share/doc/qemu/interop/objects.inv
+share/doc/qemu/interop/pr-helper.html
+share/doc/qemu/interop/qemu-ga-ref.html
+share/doc/qemu/interop/qemu-ga-ref.txt
+share/doc/qemu/interop/qemu-ga.html
+share/doc/qemu/interop/qemu-qmp-ref.html
+share/doc/qemu/interop/qemu-qmp-ref.txt
+share/doc/qemu/interop/search.html
+share/doc/qemu/interop/searchindex.js
+share/doc/qemu/interop/vhost-user-gpu.html
+share/doc/qemu/interop/vhost-user.html
+share/doc/qemu/interop/vhost-vdpa.html
+share/doc/qemu/specs/_static/alabaster.css
+share/doc/qemu/specs/_static/basic.css
+share/doc/qemu/specs/_static/custom.css
+share/doc/qemu/specs/_static/doctools.js
+share/doc/qemu/specs/_static/documentation_options.js
+share/doc/qemu/specs/_static/file.png
+share/doc/qemu/specs/_static/jquery-3.4.1.js
+share/doc/qemu/specs/_static/jquery.js
+share/doc/qemu/specs/_static/language_data.js
+share/doc/qemu/specs/_static/minus.png
+share/doc/qemu/specs/_static/plus.png
+share/doc/qemu/specs/_static/pygments.css
+share/doc/qemu/specs/_static/searchtools.js
+share/doc/qemu/specs/_static/underscore-1.3.1.js
+share/doc/qemu/specs/_static/underscore.js
+share/doc/qemu/specs/acpi_hest_ghes.html
+share/doc/qemu/specs/acpi_hw_reduced_hotplug.html
+share/doc/qemu/specs/genindex.html
+share/doc/qemu/specs/index.html
+share/doc/qemu/specs/objects.inv
+share/doc/qemu/specs/ppc-spapr-xive.html
+share/doc/qemu/specs/ppc-xive.html
+share/doc/qemu/specs/search.html
+share/doc/qemu/specs/searchindex.js
+share/doc/qemu/specs/tpm.html
+share/doc/qemu/system/.buildinfo
+share/doc/qemu/system/_static/alabaster.css
+share/doc/qemu/system/_static/basic.css
+share/doc/qemu/system/_static/custom.css
+share/doc/qemu/system/_static/doctools.js
+share/doc/qemu/system/_static/documentation_options.js
+share/doc/qemu/system/_static/file.png
+share/doc/qemu/system/_static/jquery-3.4.1.js
+share/doc/qemu/system/_static/jquery.js
+share/doc/qemu/system/_static/language_data.js
+share/doc/qemu/system/_static/minus.png
+share/doc/qemu/system/_static/plus.png
+share/doc/qemu/system/_static/pygments.css
+share/doc/qemu/system/_static/searchtools.js
+share/doc/qemu/system/_static/underscore-1.3.1.js
+share/doc/qemu/system/_static/underscore.js
+share/doc/qemu/system/arm/aspeed.html
+share/doc/qemu/system/arm/collie.html
+share/doc/qemu/system/arm/cpu-features.html
+share/doc/qemu/system/arm/digic.html
+share/doc/qemu/system/arm/gumstix.html
+share/doc/qemu/system/arm/integratorcp.html
+share/doc/qemu/system/arm/mps2.html
+share/doc/qemu/system/arm/musca.html
+share/doc/qemu/system/arm/musicpal.html
+share/doc/qemu/system/arm/nseries.html
+share/doc/qemu/system/arm/orangepi.html
+share/doc/qemu/system/arm/palm.html
+share/doc/qemu/system/arm/realview.html
+share/doc/qemu/system/arm/stellaris.html
+share/doc/qemu/system/arm/sx1.html
+share/doc/qemu/system/arm/versatile.html
+share/doc/qemu/system/arm/vexpress.html
+share/doc/qemu/system/arm/virt.html
+share/doc/qemu/system/arm/xscale.html
+share/doc/qemu/system/build-platforms.html
+share/doc/qemu/system/deprecated.html
+share/doc/qemu/system/gdb.html
+share/doc/qemu/system/genindex.html
+share/doc/qemu/system/images.html
+share/doc/qemu/system/index.html
+share/doc/qemu/system/invocation.html
+share/doc/qemu/system/ivshmem.html
+share/doc/qemu/system/keys.html
+share/doc/qemu/system/license.html
+share/doc/qemu/system/linuxboot.html
+share/doc/qemu/system/managed-startup.html
+share/doc/qemu/system/monitor.html
+share/doc/qemu/system/mux-chardev.html
+share/doc/qemu/system/net.html
+share/doc/qemu/system/objects.inv
+share/doc/qemu/system/qemu-block-drivers.html
+share/doc/qemu/system/qemu-cpu-models.html
+share/doc/qemu/system/qemu-manpage.html
+share/doc/qemu/system/quickstart.html
+share/doc/qemu/system/s390x/3270.html
+share/doc/qemu/system/s390x/css.html
+share/doc/qemu/system/s390x/protvirt.html
+share/doc/qemu/system/s390x/vfio-ap.html
+share/doc/qemu/system/s390x/vfio-ccw.html
+share/doc/qemu/system/search.html
+share/doc/qemu/system/searchindex.js
+share/doc/qemu/system/security.html
+share/doc/qemu/system/target-arm.html
+share/doc/qemu/system/target-avr.html
+share/doc/qemu/system/target-i386.html
+share/doc/qemu/system/target-m68k.html
+share/doc/qemu/system/target-mips.html
+share/doc/qemu/system/target-ppc.html
+share/doc/qemu/system/target-rx.html
+share/doc/qemu/system/target-s390x.html
+share/doc/qemu/system/target-sparc.html
+share/doc/qemu/system/target-sparc64.html
+share/doc/qemu/system/target-xtensa.html
+share/doc/qemu/system/targets.html
+share/doc/qemu/system/tls.html
+share/doc/qemu/system/usb.html
+share/doc/qemu/system/vnc-security.html
+share/doc/qemu/tools/.buildinfo
+share/doc/qemu/tools/_static/alabaster.css
+share/doc/qemu/tools/_static/basic.css
+share/doc/qemu/tools/_static/custom.css
+share/doc/qemu/tools/_static/doctools.js
+share/doc/qemu/tools/_static/documentation_options.js
+share/doc/qemu/tools/_static/file.png
+share/doc/qemu/tools/_static/jquery-3.4.1.js
+share/doc/qemu/tools/_static/jquery.js
+share/doc/qemu/tools/_static/language_data.js
+share/doc/qemu/tools/_static/minus.png
+share/doc/qemu/tools/_static/plus.png
+share/doc/qemu/tools/_static/pygments.css
+share/doc/qemu/tools/_static/searchtools.js
+share/doc/qemu/tools/_static/underscore-1.3.1.js
+share/doc/qemu/tools/_static/underscore.js
+share/doc/qemu/tools/genindex.html
+share/doc/qemu/tools/index.html
+share/doc/qemu/tools/objects.inv
+share/doc/qemu/tools/qemu-img.html
+share/doc/qemu/tools/qemu-nbd.html
+share/doc/qemu/tools/qemu-trace-stap.html
+share/doc/qemu/tools/search.html
+share/doc/qemu/tools/searchindex.js
+share/doc/qemu/tools/virtfs-proxy-helper.html
+share/doc/qemu/tools/virtiofsd.html
+share/doc/qemu/user/.buildinfo
+share/doc/qemu/user/_static/alabaster.css
+share/doc/qemu/user/_static/basic.css
+share/doc/qemu/user/_static/custom.css
+share/doc/qemu/user/_static/doctools.js
+share/doc/qemu/user/_static/documentation_options.js
+share/doc/qemu/user/_static/file.png
+share/doc/qemu/user/_static/jquery-3.4.1.js
+share/doc/qemu/user/_static/jquery.js
+share/doc/qemu/user/_static/language_data.js
+share/doc/qemu/user/_static/minus.png
+share/doc/qemu/user/_static/plus.png
+share/doc/qemu/user/_static/pygments.css
+share/doc/qemu/user/_static/searchtools.js
+share/doc/qemu/user/_static/underscore-1.3.1.js
+share/doc/qemu/user/_static/underscore.js
+share/doc/qemu/user/genindex.html
+share/doc/qemu/user/index.html
+share/doc/qemu/user/main.html
+share/doc/qemu/user/objects.inv
+share/doc/qemu/user/search.html
+share/doc/qemu/user/searchindex.js
+share/icons/hicolor/128x128/apps/qemu.png
+share/icons/hicolor/16x16/apps/qemu.png
+share/icons/hicolor/24x24/apps/qemu.png
+share/icons/hicolor/256x256/apps/qemu.png
+share/icons/hicolor/32x32/apps/qemu.bmp
+share/icons/hicolor/32x32/apps/qemu.png
+share/icons/hicolor/48x48/apps/qemu.png
+share/icons/hicolor/512x512/apps/qemu.png
+share/icons/hicolor/64x64/apps/qemu.png
+share/icons/hicolor/scalable/apps/qemu.svg
+${PLIST.gtk}share/locale/bg/LC_MESSAGES/qemu.mo
+${PLIST.gtk}share/locale/de_DE/LC_MESSAGES/qemu.mo
+${PLIST.gtk}share/locale/fr_FR/LC_MESSAGES/qemu.mo
+${PLIST.gtk}share/locale/hu/LC_MESSAGES/qemu.mo
+${PLIST.gtk}share/locale/it/LC_MESSAGES/qemu.mo
+${PLIST.gtk}share/locale/sv/LC_MESSAGES/qemu.mo
+${PLIST.gtk}share/locale/tr/LC_MESSAGES/qemu.mo
+${PLIST.gtk}share/locale/zh_CN/LC_MESSAGES/qemu.mo
+share/qemu/QEMU,cgthree.bin
+share/qemu/QEMU,tcx.bin
+share/qemu/bamboo.dtb
+share/qemu/bios-256k.bin
+share/qemu/bios-microvm.bin
+share/qemu/bios.bin
+share/qemu/canyonlands.dtb
+share/qemu/edk2-aarch64-code.fd
+share/qemu/edk2-arm-code.fd
+share/qemu/edk2-arm-vars.fd
+share/qemu/edk2-i386-code.fd
+share/qemu/edk2-i386-secure-code.fd
+share/qemu/edk2-i386-vars.fd
+share/qemu/edk2-licenses.txt
+share/qemu/edk2-x86_64-code.fd
+share/qemu/edk2-x86_64-secure-code.fd
+share/qemu/efi-e1000.rom
+share/qemu/efi-e1000e.rom
+share/qemu/efi-eepro100.rom
+share/qemu/efi-ne2k_pci.rom
+share/qemu/efi-pcnet.rom
+share/qemu/efi-rtl8139.rom
+share/qemu/efi-virtio.rom
+share/qemu/efi-vmxnet3.rom
+share/qemu/firmware/50-edk2-i386-secure.json
+share/qemu/firmware/50-edk2-x86_64-secure.json
+share/qemu/firmware/60-edk2-aarch64.json
+share/qemu/firmware/60-edk2-arm.json
+share/qemu/firmware/60-edk2-i386.json
+share/qemu/firmware/60-edk2-x86_64.json
+share/qemu/hppa-firmware.img
+share/qemu/keymaps/ar
+share/qemu/keymaps/bepo
+share/qemu/keymaps/cz
+share/qemu/keymaps/da
+share/qemu/keymaps/de
+share/qemu/keymaps/de-ch
+share/qemu/keymaps/en-gb
+share/qemu/keymaps/en-us
+share/qemu/keymaps/es
+share/qemu/keymaps/et
+share/qemu/keymaps/fi
+share/qemu/keymaps/fo
+share/qemu/keymaps/fr
+share/qemu/keymaps/fr-be
+share/qemu/keymaps/fr-ca
+share/qemu/keymaps/fr-ch
+share/qemu/keymaps/hr
+share/qemu/keymaps/hu
+share/qemu/keymaps/is
+share/qemu/keymaps/it
+share/qemu/keymaps/ja
+share/qemu/keymaps/lt
+share/qemu/keymaps/lv
+share/qemu/keymaps/mk
+share/qemu/keymaps/nl
+share/qemu/keymaps/no
+share/qemu/keymaps/pl
+share/qemu/keymaps/pt
+share/qemu/keymaps/pt-br
+share/qemu/keymaps/ru
+share/qemu/keymaps/sl
+share/qemu/keymaps/sv
+share/qemu/keymaps/th
+share/qemu/keymaps/tr
+share/qemu/kvmvapic.bin
+share/qemu/linuxboot.bin
+share/qemu/linuxboot_dma.bin
+share/qemu/multiboot.bin
+share/qemu/openbios-ppc
+share/qemu/openbios-sparc32
+share/qemu/openbios-sparc64
+share/qemu/opensbi-riscv32-sifive_u-fw_jump.bin
+share/qemu/opensbi-riscv32-virt-fw_jump.bin
+share/qemu/opensbi-riscv64-sifive_u-fw_jump.bin
+share/qemu/opensbi-riscv64-virt-fw_jump.bin
+share/qemu/palcode-clipper
+share/qemu/petalogix-ml605.dtb
+share/qemu/petalogix-s3adsp1800.dtb
+share/qemu/pvh.bin
+share/qemu/pxe-e1000.rom
+share/qemu/pxe-eepro100.rom
+share/qemu/pxe-ne2k_pci.rom
+share/qemu/pxe-pcnet.rom
+share/qemu/pxe-rtl8139.rom
+share/qemu/pxe-virtio.rom
+share/qemu/qemu-nsis.bmp
+share/qemu/qemu_vga.ndrv
+share/qemu/s390-ccw.img
+share/qemu/s390-netboot.img
+share/qemu/sgabios.bin
+share/qemu/skiboot.lid
+share/qemu/slof.bin
+share/qemu/trace-events-all
+share/qemu/u-boot-sam460-20100605.bin
+share/qemu/u-boot.e500
+share/qemu/vgabios-ati.bin
+share/qemu/vgabios-bochs-display.bin
+share/qemu/vgabios-cirrus.bin
+share/qemu/vgabios-qxl.bin
+share/qemu/vgabios-ramfb.bin
+share/qemu/vgabios-stdvga.bin
+share/qemu/vgabios-virtio.bin
+share/qemu/vgabios-vmware.bin
+share/qemu/vgabios.bin
+@pkgdir var/run
+@pkgdir include
Index: pkgsrc/emulators/qemu51/distinfo
diff -u /dev/null pkgsrc/emulators/qemu51/distinfo:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/distinfo Sat Feb 20 22:55:19 2021
@@ -0,0 +1,58 @@
+$NetBSD: distinfo,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+SHA1 (palcode-clipper) = e25ae10a10e0801e47b62b9ee2d10c8ccb4ee940
+RMD160 (palcode-clipper) = a637f1cc38dabfdff36e3f02b6dd02d7c63cb8db
+SHA512 (palcode-clipper) = 8d6966e59b59bc17c563bae3648af4ac99108990294edd0398ee91d8e61ec8f890608b9326b175d6a3a5668106b67b019a2c51b79f5b2935d4a516d34490056c
+Size (palcode-clipper) = 156704 bytes
+SHA1 (qemu-5.1.0.tar.xz) = 8c70ce2b65349e9b42bd20c9dec2c90f8e7b960a
+RMD160 (qemu-5.1.0.tar.xz) = f5e4a20c481d7e2bf822bf6bf41667b810c3cecd
+SHA512 (qemu-5.1.0.tar.xz) = e213edb71d93d5167ddce7546220ecb7b52a7778586a4f476f65bd1e510c9cfc6d1876238a7b501d9cc3fd31cc2ae4b7fb9e753bc3f12cc17cd16dfce2a96ba3
+Size (qemu-5.1.0.tar.xz) = 62911540 bytes
+SHA1 (patch-Makefile) = c5630f4221bbc9f96e04335c907ceea555b7eb26
+SHA1 (patch-accel_stubs_Makefile.objs) = 5ecdbb83e446dcbba74e1f6cf2c098e7818c0809
+SHA1 (patch-accel_stubs_nvmm-stub.c) = d66d47eabb8bb6728e777da7589b43d491adbcc8
+SHA1 (patch-backends_tpm_tpm__ioctl.h) = fbd6c877ad605f7120290efbb0ac653c69f351de
+SHA1 (patch-capstone_Makefile) = f59870031de8c4385a591362749ec82f57fd4c27
+SHA1 (patch-configure) = 2f5689b83b58066865598a83d53be2de6b42e303
+SHA1 (patch-contrib_ivshmem-client_ivshmem-client.c) = 40c8751607cbf66a37e4c4e08f2664b864e2e984
+SHA1 (patch-contrib_ivshmem-server_ivshmem-server.c) = d8f53432b5752f4263dc4ef96108a976a05147a3
+SHA1 (patch-default-configs-mips-softmmu-common.mak) = 00d6a6e2dfc590b7e4883ed122964292d667e332
+SHA1 (patch-hw-mips-Kconfig) = 359de9f0c16543f58ba9741e4f05417ad6a9f86e
+SHA1 (patch-hw-mips-Makefiles.objs) = c9d523b9310970df27d02c766225f7c22d71ae08
+SHA1 (patch-hw-mips-mipssim.c) = 7c1ad117214fe130faa95c08f25b4545ee8fe0ab
+SHA1 (patch-hw_alpha_alpha_sys.h) = 5908698208937ff9eb0bf1c504e1144af3d1bcc4
+SHA1 (patch-hw_alpha_dp264.c) = 856304784f098863728ecac3d0a9287aa22190d7
+SHA1 (patch-hw_alpha_typhoon.c) = 1bed5cd6f355c4163585c5331356ebf38c5c3a16
+SHA1 (patch-hw_core_uboot__image.h) = 17eef02349343c5fcfb7a4069cb6f8fd11efcb59
+SHA1 (patch-hw_display_omap__dss.c) = 6b13242f28e32346bc70548c216c578d98fd3420
+SHA1 (patch-hw_display_tcx.c) = 58f6c90bda734ec83b702b1b13d24c3e3219c7bd
+SHA1 (patch-hw_net_etraxfs__eth.c) = e5dd1661d60dbcd27b332403e0843500ba9544bc
+SHA1 (patch-hw_net_xilinx__axienet.c) = ebcd2676d64ce6f31e4a8c976d4fdf530ad5e8b7
+SHA1 (patch-hw_pci-host_sabre.c) = 75c076757ed96fc9f89cb0159f00c6cedcb39a27
+SHA1 (patch-hw_rtc_mc146818rtc.c) = cc7a3b28010966b65b7a16db756226ac2669f310
+SHA1 (patch-hw_scsi_scsi-disk.c) = fdbf2f962a6dcb1a115a7f8a5b8790ff9295fb33
+SHA1 (patch-hw_usb_dev-mtp.c) = 0f9034fb3904e5d5e3b98d24b94e054181687d95
+SHA1 (patch-include_sysemu_hw__accel.h) = 852bc031a1e065f614c5c913351f3e13183e00b7
+SHA1 (patch-include_sysemu_kvm.h) = 9847abe3be70bd708a521310f5d5515e45a1a5a0
+SHA1 (patch-include_sysemu_nvmm.h) = 3bd3da9b42ace0f806fabeb580f90ae19c273869
+SHA1 (patch-net_tap-solaris.c) = cc953c9a624dd55ace4e130d0b31bbfb956c17d5
+SHA1 (patch-qemu-options.hx) = e2f264117f703aa4ccf56219f370c3b1303e8b07
+SHA1 (patch-roms_qemu-palcode_hwrpb.h) = ae7b4c0680367af6f740d62a54dc86352128d76f
+SHA1 (patch-roms_qemu-palcode_init.c) = 7a0ebcd86f4106318791e7d90273fb55a424f1b8
+SHA1 (patch-roms_qemu-palcode_memcpy.c) = 7761774ae9092d0f494deaf302d663ba479a09cf
+SHA1 (patch-roms_qemu-palcode_memset.c) = 55fa4e52e03a351eb98475e7c4755e5edc409e6c
+SHA1 (patch-roms_qemu-palcode_pal.S) = 4f41194ffaeaddb39fa7bff953bd75c2f070dfa5
+SHA1 (patch-roms_qemu-palcode_pci.c) = 1d5b240fd6c940cbbe8518e4db529adba23d6fec
+SHA1 (patch-roms_qemu-palcode_pci.h) = 081c9d6d9955be24fd19455ae653339cdb133f02
+SHA1 (patch-roms_qemu-palcode_printf.c) = 7fb158f85bd1be9a939850d9d86175013f7a142b
+SHA1 (patch-roms_qemu-palcode_protos.h) = 60cf9db5544cb842207a893a78fa6bbe45af4c71
+SHA1 (patch-roms_qemu-palcode_sys-clipper.h) = 8983d7072b1c1e66bf0a18d2e49e503745692a46
+SHA1 (patch-roms_qemu-palcode_vgaio.c) = c8d7adc053cd6655f005527d16647611040c09d2
+SHA1 (patch-roms_u-boot-sam460ex_Makefile) = e43111db0c56625bc8df5e3688c242c341f3fa6a
+SHA1 (patch-roms_u-boot_tools_imx8m__image.sh) = e4c452062f40569e33aa93eec4a65bd3af2e74fc
+SHA1 (patch-softmmu_cpus.c) = 489b6ef1a37bb617d50b903dfdd6fb41a302508d
+SHA1 (patch-target_i386_Makefile.objs) = be8ab2e72521ccd0a71db6b37feb9957b27ac970
+SHA1 (patch-target_i386_helper.c) = 54363fe53688ea4030665b3bbb3ee7aba7ba5348
+SHA1 (patch-target_i386_kvm-stub.c) = 4cd2b7a8d8d8a317829f982b5acff7fdf2479d9f
+SHA1 (patch-target_i386_nvmm-all.c) = 091c56c88c2366abef907ca99e5bfa9933a2b6ab
+SHA1 (patch-target_sparc_translate.c) = 7ec2add2fd808facb48b9a66ccc345599251bf76
Index: pkgsrc/emulators/qemu51/options.mk
diff -u /dev/null pkgsrc/emulators/qemu51/options.mk:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/options.mk Sat Feb 20 22:55:19 2021
@@ -0,0 +1,91 @@
+# $NetBSD: options.mk,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+PKG_OPTIONS_VAR= PKG_OPTIONS.qemu51
+PKG_SUPPORTED_OPTIONS= debug-info gtk3 iscsi sdl spice
+PKG_SUGGESTED_OPTIONS+= iscsi spice
+
+.include "../../mk/bsd.fast.prefs.mk"
+
+.if ${OPSYS} == "Linux"
+PKG_SUPPORTED_OPTIONS+= virtfs-proxy-helper
+.endif
+
+.if ${OPSYS} != "Darwin"
+# NetBSD<9.0 does not have EGL support in native X11,
+# so the QEMU OpenGL display driver cannot build.
+. include "../../graphics/MesaLib/features.mk"
+. if !empty(MESALIB_SUPPORTS_EGL:M[Yy][Ee][Ss])
+PKG_SUPPORTED_OPTIONS+= opengl
+PKG_SUGGESTED_OPTIONS+= opengl sdl
+. else
+PKG_SUGGESTED_OPTIONS+= sdl
+. endif
+.endif
+
+.include "../../mk/bsd.options.mk"
+
+PLIST_VARS+= gtk virtfs-proxy-helper
+
+.if !empty(PKG_OPTIONS:Mdebug-info)
+CONFIGURE_ARGS+= --enable-debug-info
+.else
+CONFIGURE_ARGS+= --disable-debug-info
+.endif
+
+.if !empty(PKG_OPTIONS:Mgtk3)
+PLIST.gtk= yes
+CONFIGURE_ARGS+= --enable-gtk
+.include "../../x11/gtk3/buildlink3.mk"
+.else
+CONFIGURE_ARGS+= --disable-gtk
+.endif
+
+.if !empty(PKG_OPTIONS:Mopengl)
+CONFIGURE_ARGS+= --enable-opengl
+.include "../../graphics/MesaLib/buildlink3.mk"
+.include "../../graphics/libepoxy/buildlink3.mk"
+.else
+CONFIGURE_ARGS+= --disable-opengl
+.endif
+
+.if !empty(PKG_OPTIONS:Msdl)
+CONFIGURE_ARGS+= --enable-sdl
+.include "../../devel/SDL2/buildlink3.mk"
+.else
+CONFIGURE_ARGS+= --disable-sdl
+.endif
+
+# On Darwin, qemu uses Cocoa
+.if ${OPSYS} != "Darwin"
+.if !empty(PKG_OPTIONS:Mgtk3) || \
+ !empty(PKG_OPTIONS:Mopengl) || !empty(PKG_OPTIONS:Msdl)
+PLIST.keymap= yes
+.include "../../x11/libxkbcommon/buildlink3.mk"
+.else
+CONFIGURE_ARGS+= --disable-xkbcommon
+.endif
+.endif
+
+# NB to successfully build virtfs-proxy-helper, the upstream Linux
+# header/development libraries for libcap and libattr must be installed.
+.if !empty(PKG_OPTIONS:Mvirtfs-proxy-helper)
+PLIST.virtfs-proxy-helper= yes
+CONFIGURE_ARGS+= --enable-virtfs
+.else
+CONFIGURE_ARGS+= --disable-virtfs
+.endif
+
+.if !empty(PKG_OPTIONS:Mspice)
+CONFIGURE_ARGS+= --enable-spice
+.include "../../sysutils/spice-protocol/buildlink3.mk"
+.include "../../sysutils/spice-server/buildlink3.mk"
+.else
+CONFIGURE_ARGS+= --disable-spice
+.endif
+
+.if !empty(PKG_OPTIONS:Miscsi)
+CONFIGURE_ARGS+= --enable-libiscsi
+.include "../../net/libiscsi/buildlink3.mk"
+.else
+CONFIGURE_ARGS+= --disable-libiscsi
+.endif
Index: pkgsrc/emulators/qemu51/files/Makefile.multinode-NetBSD
diff -u /dev/null pkgsrc/emulators/qemu51/files/Makefile.multinode-NetBSD:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/files/Makefile.multinode-NetBSD Sat Feb 20 22:55:19 2021
@@ -0,0 +1,59 @@
+# $Id: Makefile.multinode-NetBSD,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+# Source: http://mail-index.NetBSD.org/netbsd-help/2005/03/25/0005.html
+#
+# Starts up two qemu instances and networks bridges them to the local
+# ethernet (ETHER_IF}. Works best with NetBSD configured to use serial
+# consoles in DISK[12]
+#
+# Usage:
+# sudo make netbsd1
+# sudo make netbsd2
+#
+# - Hubert Feyrer <hubert%feyrer.de@localhost>
+#
+
+#NETBSD_NOGFX=
+NETBSD_NOGFX= -nographic
+
+ETHER_IF= tlp0
+QEMU_RAM= 20
+DISK1= harddisk.netbsd1
+DISK2= harddisk.netbsd2
+
+
+all: netbsd1 netbsd2
+
+netbsd1: bridge
+ ifconfig tap1 create up || echo tap1: already there
+ brconfig bridge0 add tap1 up || echo tap1: already on bridge0
+ brconfig bridge0 -learn tap1 # real hub mode, step 1b
+ brconfig bridge0 flush # real hub more, step 2
+ qemu \
+ -m ${QEMU_RAM} \
+ ${NETBSD_NOGFX} \
+ -boot c \
+ -net tap,fd=3,ifname=tap1 3<>/dev/tap1 \
+ -net nic,macaddr=de:ad:be:ef:00:01 \
+ ${DISK1}
+ brconfig bridge0 delete tap1
+ ifconfig tap1 destroy
+
+netbsd2: bridge
+ ifconfig tap2 create up || echo tap2: already there
+ brconfig bridge0 add tap2 up || echo tap2: already on bridge0
+ brconfig bridge0 -learn tap2 # real hub mode, step 1c
+ brconfig bridge0 flush # real hub mode, step 2
+ qemu \
+ -m ${QEMU_RAM} \
+ ${NETBSD_NOGFX} \
+ -boot c \
+ -net tap,fd=3,ifname=tap2 3<>/dev/tap2 \
+ -net nic,macaddr=de:ad:be:ef:00:02 \
+ ${DISK2}
+ brconfig bridge0 delete tap2
+ ifconfig tap2 destroy
+
+bridge:
+ ifconfig bridge0 create || echo bridge0: already there
+ brconfig bridge0 add ${ETHER_IF} || echo bridge0: ${ETHER_IF} already there
+ brconfig bridge0 -learn ${ETHER_IF} # real hub mode, step 1a
Index: pkgsrc/emulators/qemu51/files/hw-mips-mipssim_virtio.c
diff -u /dev/null pkgsrc/emulators/qemu51/files/hw-mips-mipssim_virtio.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/files/hw-mips-mipssim_virtio.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,115 @@
+/*
+ * QEMU/mipssim-virtio extension emulation
+ *
+ * Emulates a very simple machine model similar to the one used by the
+ * proprietary MIPS emulator extended by a virtio device. The purpose is to
+ * have a better virt platform in anticipation to a readl `virt' platform for
+ * MIPS.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Reinoud Zandijk.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "cpu.h"
+#include "hw/mips/mips.h"
+#include "hw/mips/cpudevs.h"
+#include "hw/char/serial.h"
+#include "hw/isa/isa.h"
+#include "net/net.h"
+#include "sysemu/sysemu.h"
+#include "hw/boards.h"
+#include "hw/mips/bios.h"
+#include "hw/loader.h"
+#include "hw/or-irq.h"
+#include "elf.h"
+#include "hw/sysbus.h"
+#include "hw/qdev-properties.h"
+#include "exec/address-spaces.h"
+#include "qemu/error-report.h"
+#include "sysemu/qtest.h"
+#include "sysemu/reset.h"
+#include "hw/virtio/virtio-mmio.h"
+
+#define NUM_VIRTIO_TRANSPORTS 32
+#define VIRTIO_STRIDE 512
+
+#define DEV_SPACING 0x10000 /* space devices every 64k */
+#define ISA_BASE 0x1fd00000
+#define VIRTIO_MMIO_BASE (ISA_BASE + DEV_SPACING)
+
+extern void mips_mipssim_init(MachineState *machine);
+
+static void
+mips_mipssim_virtio_init(MachineState *machine)
+{
+ DeviceState *virtio_orgate;
+ MIPSCPU *cpu;
+ CPUMIPSState *env;
+
+ /* initialise parent */
+ mips_mipssim_init(machine);
+
+ cpu = MIPS_CPU(qemu_get_cpu(0));
+ env = &cpu->env;
+
+ /*
+ * TODO: in newer versions, we might need to adjust the cpu clock when its
+ * set in mips_mipssim_init()
+ */
+
+ /*
+ * virtio extention; register 32 virtio devices just after the ISA space
+ * at 0x1fd10000 with stride of 512 bytes as per i386s microvm target.
+ * register these devices in reverse order (see comments in hw/arm/virt.c)
+ */
+ virtio_orgate = DEVICE(object_new(TYPE_OR_IRQ));
+ object_property_set_int(OBJECT(virtio_orgate),
+ "num-lines", NUM_VIRTIO_TRANSPORTS, &error_fatal);
+ qdev_realize_and_unref(virtio_orgate, NULL, &error_fatal);
+
+ for (int i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
+ sysbus_create_simple("virtio-mmio",
+ VIRTIO_MMIO_BASE + i * VIRTIO_STRIDE,
+ qdev_get_gpio_in(virtio_orgate, i));
+ }
+ qdev_connect_gpio_out(DEVICE(virtio_orgate), 0, env->irq[3]);
+}
+
+static void mips_mipssim_virtio_machine_init(MachineClass *mc)
+{
+ mc->desc = "MIPS MIPSsim platform with virtio";
+ mc->init = mips_mipssim_virtio_init;
+#ifdef TARGET_MIPS64
+ mc->default_cpu_type = MIPS_CPU_TYPE_NAME("5Kf");
+#else
+ mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf");
+#endif
+ mc->default_ram_id = "mips_mipssim.ram";
+}
+
+DEFINE_MACHINE("mipssim-virtio", mips_mipssim_virtio_machine_init)
+
Index: pkgsrc/emulators/qemu51/patches/patch-Makefile
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-Makefile:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-Makefile Sat Feb 20 22:55:19 2021
@@ -0,0 +1,12 @@
+$NetBSD: patch-Makefile,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+--- Makefile.orig 2020-08-11 19:17:15.000000000 +0000
++++ Makefile
+@@ -530,6 +530,7 @@ $(TARGET_DIRS_RULES):
+ DTC_MAKE_ARGS=-I$(SRC_PATH)/dtc VPATH=$(SRC_PATH)/dtc -C dtc V="$(V)" LIBFDT_lib=""
+ DTC_CFLAGS=$(CFLAGS) $(QEMU_CFLAGS)
+ DTC_CPPFLAGS=-I$(SRC_PATH)/dtc/libfdt
++ARFLAGS= -rcs
+
+ .PHONY: dtc/all
+ dtc/all: .git-submodule-status dtc/libfdt
Index: pkgsrc/emulators/qemu51/patches/patch-accel_stubs_Makefile.objs
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-accel_stubs_Makefile.objs:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-accel_stubs_Makefile.objs Sat Feb 20 22:55:19 2021
@@ -0,0 +1,14 @@
+$NetBSD: patch-accel_stubs_Makefile.objs,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Add NVMM support.
+
+--- accel/stubs/Makefile.objs.orig 2020-08-11 19:17:15.000000000 +0000
++++ accel/stubs/Makefile.objs
+@@ -1,6 +1,7 @@
+ obj-$(call lnot,$(CONFIG_HAX)) += hax-stub.o
+ obj-$(call lnot,$(CONFIG_HVF)) += hvf-stub.o
+ obj-$(call lnot,$(CONFIG_WHPX)) += whpx-stub.o
++obj-$(call lnot,$(CONFIG_NVMM)) += nvmm-stub.o
+ obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
+ obj-$(call lnot,$(CONFIG_TCG)) += tcg-stub.o
+ obj-$(call lnot,$(CONFIG_XEN)) += xen-stub.o
Index: pkgsrc/emulators/qemu51/patches/patch-accel_stubs_nvmm-stub.c
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-accel_stubs_nvmm-stub.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-accel_stubs_nvmm-stub.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,50 @@
+$NetBSD: patch-accel_stubs_nvmm-stub.c,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Add NVMM support.
+
+--- accel/stubs/nvmm-stub.c.orig 2020-02-06 16:25:13.966864001 +0000
++++ accel/stubs/nvmm-stub.c
+@@ -0,0 +1,43 @@
++/*
++ * Copyright (c) 2018-2019 Maxime Villard, All rights reserved.
++ *
++ * NetBSD Virtual Machine Monitor (NVMM) accelerator stub.
++ *
++ * This work is licensed under the terms of the GNU GPL, version 2 or later.
++ * See the COPYING file in the top-level directory.
++ */
++
++#include "qemu/osdep.h"
++#include "qemu-common.h"
++#include "cpu.h"
++#include "sysemu/nvmm.h"
++
++int nvmm_init_vcpu(CPUState *cpu)
++{
++ return -1;
++}
++
++int nvmm_vcpu_exec(CPUState *cpu)
++{
++ return -1;
++}
++
++void nvmm_destroy_vcpu(CPUState *cpu)
++{
++}
++
++void nvmm_cpu_synchronize_state(CPUState *cpu)
++{
++}
++
++void nvmm_cpu_synchronize_post_reset(CPUState *cpu)
++{
++}
++
++void nvmm_cpu_synchronize_post_init(CPUState *cpu)
++{
++}
++
++void nvmm_cpu_synchronize_pre_loadvm(CPUState *cpu)
++{
++}
Index: pkgsrc/emulators/qemu51/patches/patch-backends_tpm_tpm__ioctl.h
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-backends_tpm_tpm__ioctl.h:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-backends_tpm_tpm__ioctl.h Sat Feb 20 22:55:19 2021
@@ -0,0 +1,16 @@
+$NetBSD: patch-backends_tpm_tpm__ioctl.h,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+SunOS needs filio.h for _IO*() macros.
+
+--- backends/tpm/tpm_ioctl.h.orig 2019-08-15 19:01:42.000000000 +0000
++++ backends/tpm/tpm_ioctl.h
+@@ -9,6 +9,9 @@
+ #ifndef TPM_IOCTL_H
+ #define TPM_IOCTL_H
+
++#ifdef __sun
++#include <sys/filio.h>
++#endif
+ #include <sys/uio.h>
+ #include <sys/ioctl.h>
+
Index: pkgsrc/emulators/qemu51/patches/patch-capstone_Makefile
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-capstone_Makefile:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-capstone_Makefile Sat Feb 20 22:55:19 2021
@@ -0,0 +1,17 @@
+$NetBSD: patch-capstone_Makefile,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Support greps that do not support -m.
+
+--- capstone/Makefile.orig 2019-08-15 19:04:33.000000000 +0000
++++ capstone/Makefile
+@@ -254,8 +254,8 @@ PKGCFGDIR ?= $(LIBDATADIR)/pkgconfig
+ API_MAJOR=$(shell echo `grep -e CS_API_MAJOR include/capstone.h | grep -v = | awk '{print $$3}'` | awk '{print $$1}')
+ VERSION_EXT =
+
+-IS_APPLE := $(shell $(CC) -dM -E - < /dev/null | grep -cm 1 -e __apple_build_version__ -e __APPLE_CC__)
+-ifeq ($(IS_APPLE),1)
++IS_APPLE := $(shell $(CC) -dM -E - < /dev/null | grep -c -e __apple_build_version__ -e __APPLE_CC__)
++ifneq ($(IS_APPLE),0)
+ # on MacOS, compile in Universal format by default
+ MACOS_UNIVERSAL ?= yes
+ ifeq ($(MACOS_UNIVERSAL),yes)
Index: pkgsrc/emulators/qemu51/patches/patch-configure
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-configure:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-configure Sat Feb 20 22:55:19 2021
@@ -0,0 +1,121 @@
+$NetBSD: patch-configure,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Add NVMM support.
+Fix jemalloc detection.
+
+--- configure.orig 2020-08-11 19:17:15.000000000 +0000
++++ configure
+@@ -246,6 +246,17 @@ supported_whpx_target() {
+ return 1
+ }
+
++supported_nvmm_target() {
++ test "$nvmm" = "yes" || return 1
++ glob "$1" "*-softmmu" || return 1
++ case "${1%-softmmu}" in
++ i386|x86_64)
++ return 0
++ ;;
++ esac
++ return 1
++}
++
+ supported_target() {
+ case "$1" in
+ *-softmmu)
+@@ -273,6 +284,7 @@ supported_target() {
+ supported_hax_target "$1" && return 0
+ supported_hvf_target "$1" && return 0
+ supported_whpx_target "$1" && return 0
++ supported_nvmm_target "$1" && return 0
+ print_error "TCG disabled, but hardware accelerator not available for '$target'"
+ return 1
+ }
+@@ -395,6 +407,7 @@ kvm="no"
+ hax="no"
+ hvf="no"
+ whpx="no"
++nvmm="no"
+ rdma=""
+ pvrdma=""
+ gprof="no"
+@@ -847,6 +860,7 @@ DragonFly)
+ NetBSD)
+ bsd="yes"
+ hax="yes"
++ nvmm=""
+ make="${MAKE-gmake}"
+ audio_drv_list="oss try-sdl"
+ audio_possible_drivers="oss sdl"
+@@ -1233,6 +1247,10 @@ for opt do
+ ;;
+ --enable-whpx) whpx="yes"
+ ;;
++ --disable-nvmm) nvmm="no"
++ ;;
++ --enable-nvmm) nvmm="yes"
++ ;;
+ --disable-tcg-interpreter) tcg_interpreter="no"
+ ;;
+ --enable-tcg-interpreter) tcg_interpreter="yes"
+@@ -1879,6 +1897,7 @@ disabled with --disable-FEATURE, default
+ hax HAX acceleration support
+ hvf Hypervisor.framework acceleration support
+ whpx Windows Hypervisor Platform acceleration support
++ nvmm NetBSD Virtual Machine Monitor acceleration support
+ rdma Enable RDMA-based migration
+ pvrdma Enable PVRDMA support
+ vde support for vde network
+@@ -2966,6 +2985,20 @@ if test "$whpx" != "no" ; then
+ fi
+
+ ##########################################
++# NetBSD Virtual Machine Monitor (NVMM) accelerator check
++if test "$nvmm" != "no" ; then
++ if check_include "nvmm.h" ; then
++ nvmm="yes"
++ LIBS="-lnvmm $LIBS"
++ else
++ if test "$nvmm" = "yes"; then
++ feature_not_found "NVMM" "NVMM is not available"
++ fi
++ nvmm="no"
++ fi
++fi
++
++##########################################
+ # Sparse probe
+ if test "$sparse" != "no" ; then
+ if has cgcc; then
+@@ -4736,8 +4769,11 @@ int main(void) {
+ }
+ EOF
+
+- if compile_prog "" "-ljemalloc" ; then
+- LIBS="-ljemalloc $LIBS"
++ jemalloc_cflags=$($pkg_config --cflags jemalloc)
++ jemalloc_libs=$($pkg_config --libs jemalloc)
++ if compile_prog "" "$jemalloc_libs" ; then
++ LIBS="$jemalloc_libs $LIBS"
++ QEMU_CFLAGS="$QEMU_CFLAGS $jemalloc_cflags"
+ else
+ feature_not_found "jemalloc" "install jemalloc devel"
+ fi
+@@ -6934,6 +6970,7 @@ echo "KVM support $kvm"
+ echo "HAX support $hax"
+ echo "HVF support $hvf"
+ echo "WHPX support $whpx"
++echo "NVMM support $nvmm"
+ echo "TCG support $tcg"
+ if test "$tcg" = "yes" ; then
+ echo "TCG debug enabled $debug_tcg"
+@@ -8332,6 +8369,9 @@ fi
+ if test "$target_aligned_only" = "yes" ; then
+ echo "TARGET_ALIGNED_ONLY=y" >> $config_target_mak
+ fi
++if supported_nvmm_target $target; then
++ echo "CONFIG_NVMM=y" >> $config_target_mak
++fi
+ if test "$target_bigendian" = "yes" ; then
+ echo "TARGET_WORDS_BIGENDIAN=y" >> $config_target_mak
+ fi
Index: pkgsrc/emulators/qemu51/patches/patch-contrib_ivshmem-client_ivshmem-client.c
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-contrib_ivshmem-client_ivshmem-client.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-contrib_ivshmem-client_ivshmem-client.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,37 @@
+$NetBSD: patch-contrib_ivshmem-client_ivshmem-client.c,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Avoid sun definition.
+
+--- contrib/ivshmem-client/ivshmem-client.c.orig 2017-04-20 14:57:00.000000000 +0000
++++ contrib/ivshmem-client/ivshmem-client.c
+@@ -179,7 +179,7 @@ ivshmem_client_init(IvshmemClient *clien
+ int
+ ivshmem_client_connect(IvshmemClient *client)
+ {
+- struct sockaddr_un sun;
++ struct sockaddr_un sockun;
+ int fd, ret;
+ int64_t tmp;
+
+@@ -193,16 +193,16 @@ ivshmem_client_connect(IvshmemClient *cl
+ return -1;
+ }
+
+- sun.sun_family = AF_UNIX;
+- ret = snprintf(sun.sun_path, sizeof(sun.sun_path), "%s",
++ sockun.sun_family = AF_UNIX;
++ ret = snprintf(sockun.sun_path, sizeof(sockun.sun_path), "%s",
+ client->unix_sock_path);
+- if (ret < 0 || ret >= sizeof(sun.sun_path)) {
++ if (ret < 0 || ret >= sizeof(sockun.sun_path)) {
+ IVSHMEM_CLIENT_DEBUG(client, "could not copy unix socket path\n");
+ goto err_close;
+ }
+
+- if (connect(client->sock_fd, (struct sockaddr *)&sun, sizeof(sun)) < 0) {
+- IVSHMEM_CLIENT_DEBUG(client, "cannot connect to %s: %s\n", sun.sun_path,
++ if (connect(client->sock_fd, (struct sockaddr *)&sockun, sizeof(sockun)) < 0) {
++ IVSHMEM_CLIENT_DEBUG(client, "cannot connect to %s: %s\n", sockun.sun_path,
+ strerror(errno));
+ goto err_close;
+ }
Index: pkgsrc/emulators/qemu51/patches/patch-contrib_ivshmem-server_ivshmem-server.c
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-contrib_ivshmem-server_ivshmem-server.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-contrib_ivshmem-server_ivshmem-server.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,36 @@
+$NetBSD: patch-contrib_ivshmem-server_ivshmem-server.c,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Avoid sun definition.
+
+--- contrib/ivshmem-server/ivshmem-server.c.orig 2017-04-20 14:57:00.000000000 +0000
++++ contrib/ivshmem-server/ivshmem-server.c
+@@ -289,7 +289,7 @@ ivshmem_server_init(IvshmemServer *serve
+ int
+ ivshmem_server_start(IvshmemServer *server)
+ {
+- struct sockaddr_un sun;
++ struct sockaddr_un sockun;
+ int shm_fd, sock_fd, ret;
+
+ /* open shm file */
+@@ -328,15 +328,15 @@ ivshmem_server_start(IvshmemServer *serv
+ goto err_close_shm;
+ }
+
+- sun.sun_family = AF_UNIX;
+- ret = snprintf(sun.sun_path, sizeof(sun.sun_path), "%s",
++ sockun.sun_family = AF_UNIX;
++ ret = snprintf(sockun.sun_path, sizeof(sockun.sun_path), "%s",
+ server->unix_sock_path);
+- if (ret < 0 || ret >= sizeof(sun.sun_path)) {
++ if (ret < 0 || ret >= sizeof(sockun.sun_path)) {
+ IVSHMEM_SERVER_DEBUG(server, "could not copy unix socket path\n");
+ goto err_close_sock;
+ }
+- if (bind(sock_fd, (struct sockaddr *)&sun, sizeof(sun)) < 0) {
+- IVSHMEM_SERVER_DEBUG(server, "cannot connect to %s: %s\n", sun.sun_path,
++ if (bind(sock_fd, (struct sockaddr *)&sockun, sizeof(sockun)) < 0) {
++ IVSHMEM_SERVER_DEBUG(server, "cannot connect to %s: %s\n", sockun.sun_path,
+ strerror(errno));
+ goto err_close_sock;
+ }
Index: pkgsrc/emulators/qemu51/patches/patch-default-configs-mips-softmmu-common.mak
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-default-configs-mips-softmmu-common.mak:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-default-configs-mips-softmmu-common.mak Sat Feb 20 22:55:19 2021
@@ -0,0 +1,12 @@
+$NetBSD: patch-default-configs-mips-softmmu-common.mak,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+--- default-configs/mips-softmmu-common.mak.orig 2020-08-11 19:17:14.000000000 +0000
++++ default-configs/mips-softmmu-common.mak
+@@ -37,6 +37,7 @@ CONFIG_R4K=y
+ CONFIG_MALTA=y
+ CONFIG_PCNET_PCI=y
+ CONFIG_MIPSSIM=y
++CONFIG_MIPSSIM_VIRTIO=y
+ CONFIG_ACPI_SMBUS=y
+ CONFIG_SMBUS_EEPROM=y
+ CONFIG_TEST_DEVICES=y
Index: pkgsrc/emulators/qemu51/patches/patch-hw-mips-Kconfig
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-hw-mips-Kconfig:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-hw-mips-Kconfig Sat Feb 20 22:55:19 2021
@@ -0,0 +1,19 @@
+$NetBSD: patch-hw-mips-Kconfig,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+--- hw/mips/Kconfig.orig 2020-08-11 19:17:15.000000000 +0000
++++ hw/mips/Kconfig
+@@ -21,6 +21,14 @@ config MIPSSIM
+ select SERIAL_ISA
+ select MIPSNET
+
++config MIPSSIM_VIRTIO
++ bool
++ select ISA_BUS
++ select SERIAL_ISA
++ select MIPSNET
++ select VIRTIO_MMIO
++ select OR_IRQ
++
+ config JAZZ
+ bool
+ select ISA_BUS
Index: pkgsrc/emulators/qemu51/patches/patch-hw-mips-Makefiles.objs
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-hw-mips-Makefiles.objs:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-hw-mips-Makefiles.objs Sat Feb 20 22:55:19 2021
@@ -0,0 +1,12 @@
+$NetBSD: patch-hw-mips-Makefiles.objs,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+--- hw/mips/Makefile.objs.orig 2020-08-11 19:17:15.000000000 +0000
++++ hw/mips/Makefile.objs
+@@ -2,6 +2,7 @@ obj-y += addr.o mips_int.o
+ obj-$(CONFIG_R4K) += r4k.o
+ obj-$(CONFIG_MALTA) += gt64xxx_pci.o malta.o
+ obj-$(CONFIG_MIPSSIM) += mipssim.o
++obj-$(CONFIG_MIPSSIM_VIRTIO) += mipssim_virtio.o
+ obj-$(CONFIG_JAZZ) += jazz.o
+ obj-$(CONFIG_FULOONG) += fuloong2e.o
+ obj-$(CONFIG_MIPS_CPS) += cps.o
Index: pkgsrc/emulators/qemu51/patches/patch-hw-mips-mipssim.c
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-hw-mips-mipssim.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-hw-mips-mipssim.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,23 @@
+$NetBSD: patch-hw-mips-mipssim.c,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+--- hw/mips/mipssim.c.orig 2020-08-11 19:17:15.000000000 +0000
++++ hw/mips/mipssim.c
+@@ -46,6 +46,8 @@
+ #include "sysemu/qtest.h"
+ #include "sysemu/reset.h"
+
++void mips_mipssim_init(MachineState *);
++
+ static struct _loaderparams {
+ int ram_size;
+ const char *kernel_filename;
+@@ -140,8 +142,7 @@ static void mipsnet_init(int base, qemu_
+ sysbus_mmio_get_region(s, 0));
+ }
+
+-static void
+-mips_mipssim_init(MachineState *machine)
++void mips_mipssim_init(MachineState *machine)
+ {
+ const char *kernel_filename = machine->kernel_filename;
+ const char *kernel_cmdline = machine->kernel_cmdline;
Index: pkgsrc/emulators/qemu51/patches/patch-hw_alpha_alpha_sys.h
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-hw_alpha_alpha_sys.h:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-hw_alpha_alpha_sys.h Sat Feb 20 22:55:19 2021
@@ -0,0 +1,15 @@
+$NetBSD: patch-hw_alpha_alpha_sys.h,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Pass 'devfn_min' argument to typhoon_init().
+
+--- hw/alpha/alpha_sys.h.orig 2020-10-01 00:17:37.231192966 +0000
++++ hw/alpha/alpha_sys.h 2020-10-01 00:17:49.188425709 +0000
+@@ -11,7 +11,7 @@
+
+
+ PCIBus *typhoon_init(MemoryRegion *, ISABus **, qemu_irq *, AlphaCPU *[4],
+- pci_map_irq_fn);
++ pci_map_irq_fn, uint8_t devfn_min);
+
+ /* alpha_pci.c. */
+ extern const MemoryRegionOps alpha_pci_ignore_ops;
Index: pkgsrc/emulators/qemu51/patches/patch-hw_alpha_dp264.c
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-hw_alpha_dp264.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-hw_alpha_dp264.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,39 @@
+$NetBSD: patch-hw_alpha_dp264.c,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Because we're using CLIPPER IRQ mappings, the minimum PCI device
+IdSel is 1. Pass that to typhoon_init().
+
+Set bit 6 in trap_arg2 to tell the PALcode that the -nographic option
+was specified. This is used by the PALcode to initialize the CTB for
+serial console.
+
+--- hw/alpha/dp264.c.orig 2020-08-11 19:17:14.000000000 +0000
++++ hw/alpha/dp264.c 2020-10-02 15:52:10.654767858 +0000
+@@ -72,13 +72,25 @@ static void clipper_init(MachineState *m
+ cpus[i] = ALPHA_CPU(cpu_create(machine->cpu_type));
+ }
+
++ /* arg0 -> memory size
++ arg1 -> kernel entry point
++ arg2 -> config word
++
++ Config word: bits 0-5 -> ncpus
++ bit 6 -> nographics option (for HWRPB CTB)
++
++ See init_hwrpb() in the PALcode. */
++
+ cpus[0]->env.trap_arg0 = ram_size;
+ cpus[0]->env.trap_arg1 = 0;
+ cpus[0]->env.trap_arg2 = smp_cpus;
++ if (!machine->enable_graphics)
++ cpus[0]->env.trap_arg2 |= (1 << 6);
+
+- /* Init the chipset. */
++ /* Init the chipset. Because we're using CLIPPER IRQ mappings,
++ the minimum PCI device IdSel is 1. */
+ pci_bus = typhoon_init(machine->ram, &isa_bus, &rtc_irq, cpus,
+- clipper_pci_map_irq);
++ clipper_pci_map_irq, PCI_DEVFN(1, 0));
+
+ /* Since we have an SRM-compatible PALcode, use the SRM epoch. */
+ mc146818_rtc_init(isa_bus, 1900, rtc_irq);
Index: pkgsrc/emulators/qemu51/patches/patch-hw_alpha_typhoon.c
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-hw_alpha_typhoon.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-hw_alpha_typhoon.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,148 @@
+$NetBSD: patch-hw_alpha_typhoon.c,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Allow callers of typhoon_init() to specify a minimum PCI devfn.
+
+Add a minimal i82378 SIO PCI node so that NetBSD/alpha will find
+and probe the ISA bus.
+
+--- hw/alpha/typhoon.c.orig 2020-10-01 00:34:35.392982214 +0000
++++ hw/alpha/typhoon.c 2020-10-01 00:53:13.419539599 +0000
+@@ -817,7 +817,8 @@ static void typhoon_alarm_timer(void *op
+ }
+
+ PCIBus *typhoon_init(MemoryRegion *ram, ISABus **isa_bus, qemu_irq *p_rtc_irq,
+- AlphaCPU *cpus[4], pci_map_irq_fn sys_map_irq)
++ AlphaCPU *cpus[4], pci_map_irq_fn sys_map_irq,
++ uint8_t devfn_min)
+ {
+ MemoryRegion *addr_space = get_system_memory();
+ DeviceState *dev;
+@@ -887,7 +888,7 @@ PCIBus *typhoon_init(MemoryRegion *ram,
+ b = pci_register_root_bus(dev, "pci",
+ typhoon_set_irq, sys_map_irq, s,
+ &s->pchip.reg_mem, &s->pchip.reg_io,
+- 0, 64, TYPE_PCI_BUS);
++ devfn_min, 64, TYPE_PCI_BUS);
+ phb->bus = b;
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+
+@@ -921,10 +922,21 @@ PCIBus *typhoon_init(MemoryRegion *ram,
+ /* Pchip1 PCI configuration, 0x802.FE00.0000, 16MB. */
+
+ /* Init the ISA bus. */
+- /* ??? Technically there should be a cy82c693ub pci-isa bridge. */
++ /* Init the PCI-ISA bridge. Technically, this would have been
++ a cy82c693ub, but a i82378 SIO was also used on many Alpha
++ systems and is close enough.
++
++ ??? We are using a private, stripped down implementation of i82378
++ so that we can handle the way the ISA interrupts are wired up on
++ Tsunami-type systems. We're leaving that (and the rest of the board
++ peripheral setup) untoucned; we merely need to instantiate the PCI
++ device node for the bridge, so that operating systems that expect
++ it to be there will see it. */
+ {
+ qemu_irq *isa_irqs;
+
++ pci_create_simple(b, PCI_DEVFN(7, 0), "i82378-typhoon");
++
+ *isa_bus = isa_bus_new(NULL, get_system_memory(), &s->pchip.reg_io,
+ &error_abort);
+ isa_irqs = i8259_init(*isa_bus,
+@@ -955,10 +967,96 @@ static const TypeInfo typhoon_iommu_memo
+ .class_init = typhoon_iommu_memory_region_class_init,
+ };
+
++/* The following was copied from hw/isa/i82378.c and modified to provide
++ only the minimal PCI device node. */
++
++/*
++ * QEMU Intel i82378 emulation (PCI to ISA bridge)
++ *
++ * Copyright (c) 2010-2011 Herv\xc3\xa9 Poussineau
++ *
++ * This library is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU Lesser General Public
++ * License as published by the Free Software Foundation; either
++ * version 2 of the License, or (at your option) any later version.
++ *
++ * This library is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * Lesser General Public License for more details.
++ *
++ * You should have received a copy of the GNU Lesser General Public
++ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include "migration/vmstate.h"
++
++#define TYPE_I82378 "i82378-typhoon"
++#define I82378(obj) \
++ OBJECT_CHECK(I82378State, (obj), TYPE_I82378)
++
++typedef struct I82378State {
++ PCIDevice parent_obj;
++} I82378State;
++
++static const VMStateDescription vmstate_i82378 = {
++ .name = "pci-i82378-typhoon",
++ .version_id = 0,
++ .minimum_version_id = 0,
++ .fields = (VMStateField[]) {
++ VMSTATE_PCI_DEVICE(parent_obj, I82378State),
++ VMSTATE_END_OF_LIST()
++ },
++};
++
++static void i82378_realize(PCIDevice *pci, Error **errp)
++{
++ uint8_t *pci_conf;
++
++ pci_conf = pci->config;
++ pci_set_word(pci_conf + PCI_COMMAND,
++ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
++ pci_set_word(pci_conf + PCI_STATUS,
++ PCI_STATUS_DEVSEL_MEDIUM);
++
++ pci_config_set_interrupt_pin(pci_conf, 1); /* interrupt pin 0 */
++}
++
++static void i82378_init(Object *obj)
++{
++}
++
++static void i82378_class_init(ObjectClass *klass, void *data)
++{
++ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
++ DeviceClass *dc = DEVICE_CLASS(klass);
++
++ k->realize = i82378_realize;
++ k->vendor_id = PCI_VENDOR_ID_INTEL;
++ k->device_id = PCI_DEVICE_ID_INTEL_82378;
++ k->revision = 0x03;
++ k->class_id = PCI_CLASS_BRIDGE_ISA;
++ dc->vmsd = &vmstate_i82378;
++ set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
++}
++
++static const TypeInfo i82378_typhoon_type_info = {
++ .name = TYPE_I82378,
++ .parent = TYPE_PCI_DEVICE,
++ .instance_size = sizeof(I82378State),
++ .instance_init = i82378_init,
++ .class_init = i82378_class_init,
++ .interfaces = (InterfaceInfo[]) {
++ { INTERFACE_CONVENTIONAL_PCI_DEVICE },
++ { },
++ },
++};
++
+ static void typhoon_register_types(void)
+ {
+ type_register_static(&typhoon_pcihost_info);
+ type_register_static(&typhoon_iommu_memory_region_info);
++ type_register_static(&i82378_typhoon_type_info);
+ }
+
+ type_init(typhoon_register_types)
Index: pkgsrc/emulators/qemu51/patches/patch-hw_core_uboot__image.h
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-hw_core_uboot__image.h:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-hw_core_uboot__image.h Sat Feb 20 22:55:19 2021
@@ -0,0 +1,12 @@
+$NetBSD: patch-hw_core_uboot__image.h,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+--- hw/core/uboot_image.h.orig 2019-04-23 18:14:45.000000000 +0000
++++ hw/core/uboot_image.h
+@@ -75,6 +75,7 @@
+ #define IH_CPU_NIOS2 15 /* Nios-II */
+ #define IH_CPU_BLACKFIN 16 /* Blackfin */
+ #define IH_CPU_AVR32 17 /* AVR32 */
++#define IH_CPU_ARM64 22 /* ARM64 */
+
+ /*
+ * Image Types
Index: pkgsrc/emulators/qemu51/patches/patch-hw_display_omap__dss.c
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-hw_display_omap__dss.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-hw_display_omap__dss.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,30 @@
+$NetBSD: patch-hw_display_omap__dss.c,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Avoid conflicts with SSP read() macro in NetBSD's <ssp/unistd.h>
+(PR lib/43832: ssp causes common names to be defines)
+
+--- hw/display/omap_dss.c.orig 2013-11-27 22:15:55.000000000 +0000
++++ hw/display/omap_dss.c
+@@ -791,18 +791,18 @@ static void omap_rfbi_write(void *opaque
+ break;
+ case 0x58: /* RFBI_READ */
+ if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
+- s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 1);
++ s->rfbi.rxbuf = (*s->rfbi.chip[0]->read)(s->rfbi.chip[0]->opaque, 1);
+ else if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
+- s->rfbi.rxbuf = s->rfbi.chip[1]->read(s->rfbi.chip[1]->opaque, 1);
++ s->rfbi.rxbuf = (*s->rfbi.chip[1]->read)(s->rfbi.chip[1]->opaque, 1);
+ if (!-- s->rfbi.pixels)
+ omap_rfbi_transfer_stop(s);
+ break;
+
+ case 0x5c: /* RFBI_STATUS */
+ if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
+- s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 0);
++ s->rfbi.rxbuf = (*s->rfbi.chip[0]->read)(s->rfbi.chip[0]->opaque, 0);
+ else if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
+- s->rfbi.rxbuf = s->rfbi.chip[1]->read(s->rfbi.chip[1]->opaque, 0);
++ s->rfbi.rxbuf = (*s->rfbi.chip[1]->read)(s->rfbi.chip[1]->opaque, 0);
+ if (!-- s->rfbi.pixels)
+ omap_rfbi_transfer_stop(s);
+ break;
Index: pkgsrc/emulators/qemu51/patches/patch-hw_display_tcx.c
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-hw_display_tcx.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-hw_display_tcx.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,54 @@
+$NetBSD: patch-hw_display_tcx.c,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Fix for https://bugs.launchpad.net/qemu/+bug/1892540/
+by Philippe Mathieu-Daude.
+
+--- hw/display/tcx.c.orig 2020-08-11 19:17:15.000000000 +0000
++++ hw/display/tcx.c
+@@ -548,20 +548,28 @@ static const MemoryRegionOps tcx_stip_op
+ .read = tcx_stip_readl,
+ .write = tcx_stip_writel,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+- .valid = {
++ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
++ .valid = {
++ .min_access_size = 4,
++ .max_access_size = 8,
++ },
+ };
+
+ static const MemoryRegionOps tcx_rstip_ops = {
+ .read = tcx_stip_readl,
+ .write = tcx_rstip_writel,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+- .valid = {
++ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
++ .valid = {
++ .min_access_size = 4,
++ .max_access_size = 8,
++ },
+ };
+
+ static uint64_t tcx_blit_readl(void *opaque, hwaddr addr,
+@@ -650,10 +658,14 @@ static const MemoryRegionOps tcx_rblit_o
+ .read = tcx_blit_readl,
+ .write = tcx_rblit_writel,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+- .valid = {
++ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
++ .valid = {
++ .min_access_size = 4,
++ .max_access_size = 8,
++ },
+ };
+
+ static void tcx_invalidate_cursor_position(TCXState *s)
Index: pkgsrc/emulators/qemu51/patches/patch-hw_net_etraxfs__eth.c
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-hw_net_etraxfs__eth.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-hw_net_etraxfs__eth.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,25 @@
+$NetBSD: patch-hw_net_etraxfs__eth.c,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Avoid conflicts with SSP read() macro in NetBSD's <ssp/unistd.h>
+(PR lib/43832: ssp causes common names to be defines)
+
+--- hw/net/etraxfs_eth.c.orig 2013-11-27 22:15:55.000000000 +0000
++++ hw/net/etraxfs_eth.c
+@@ -185,7 +185,7 @@ static void mdio_read_req(struct qemu_md
+
+ phy = bus->devs[bus->addr];
+ if (phy && phy->read) {
+- bus->data = phy->read(phy, bus->req);
++ bus->data = (*phy->read)(phy, bus->req);
+ } else {
+ bus->data = 0xffff;
+ }
+@@ -364,7 +364,7 @@ static void eth_validate_duplex(ETRAXFSE
+ int new_mm = 0;
+
+ phy = eth->mdio_bus.devs[eth->phyaddr];
+- phy_duplex = !!(phy->read(phy, 18) & (1 << 11));
++ phy_duplex = !!((*phy->read)(phy, 18) & (1 << 11));
+ mac_duplex = !!(eth->regs[RW_REC_CTRL] & 128);
+
+ if (mac_duplex != phy_duplex) {
Index: pkgsrc/emulators/qemu51/patches/patch-hw_net_xilinx__axienet.c
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-hw_net_xilinx__axienet.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-hw_net_xilinx__axienet.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,16 @@
+$NetBSD: patch-hw_net_xilinx__axienet.c,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Avoid conflicts with SSP read() macro in NetBSD's <ssp/unistd.h>
+(PR lib/43832: ssp causes common names to be defines)
+
+--- hw/net/xilinx_axienet.c.orig 2013-11-27 22:15:55.000000000 +0000
++++ hw/net/xilinx_axienet.c
+@@ -207,7 +207,7 @@ static uint16_t mdio_read_req(struct MDI
+
+ phy = bus->devs[addr];
+ if (phy && phy->read) {
+- data = phy->read(phy, reg);
++ data = (*phy->read)(phy, reg);
+ } else {
+ data = 0xffff;
+ }
Index: pkgsrc/emulators/qemu51/patches/patch-hw_pci-host_sabre.c
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-hw_pci-host_sabre.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-hw_pci-host_sabre.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,16 @@
+$NetBSD: patch-hw_pci-host_sabre.c,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Legacy OBIO IRQs on sabre have numbers between 32 and 64, so raise
+number of IRQs to 64. Fixes PR 54310.
+
+--- hw/pci-host/sabre.c.orig 2020-08-11 21:17:15.000000000 +0200
++++ hw/pci-host/sabre.c 2020-10-10 17:37:52.445284000 +0200
+@@ -396,7 +396,7 @@
+ pci_sabre_set_irq, pci_sabre_map_irq, s,
+ &s->pci_mmio,
+ &s->pci_ioport,
+- 0, 32, TYPE_PCI_BUS);
++ 0, 64, TYPE_PCI_BUS);
+
+ pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE);
+
Index: pkgsrc/emulators/qemu51/patches/patch-hw_rtc_mc146818rtc.c
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-hw_rtc_mc146818rtc.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-hw_rtc_mc146818rtc.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,32 @@
+$NetBSD: patch-hw_rtc_mc146818rtc.c,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Ensure the periodic timer is started as soon as the device is realized,
+and follow the real hardware's lead of updating the PF bit in REG_C even
+if it's not going to result in raising an interrupt.
+
+--- hw/rtc/mc146818rtc.c.orig 2020-10-01 00:56:55.574093880 +0000
++++ hw/rtc/mc146818rtc.c 2020-10-01 00:58:40.326479896 +0000
+@@ -155,9 +155,15 @@ static uint32_t rtc_periodic_clock_ticks
+ {
+ int period_code;
+
++#if 0
++ /*
++ * Real hardware sets the PF bit rergardless if it actually
++ * raises an interrupt.
++ */
+ if (!(s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
+ return 0;
+ }
++#endif
+
+ period_code = s->cmos_data[RTC_REG_A] & 0x0f;
+
+@@ -944,6 +950,7 @@ static void rtc_realizefn(DeviceState *d
+ }
+
+ s->periodic_timer = timer_new_ns(rtc_clock, rtc_periodic_timer, s);
++ periodic_timer_update(s, qemu_clock_get_ns(rtc_clock), 0, true);
+ s->update_timer = timer_new_ns(rtc_clock, rtc_update_timer, s);
+ check_update_timer(s);
+
Index: pkgsrc/emulators/qemu51/patches/patch-hw_scsi_scsi-disk.c
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-hw_scsi_scsi-disk.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-hw_scsi_scsi-disk.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,50 @@
+$NetBSD: patch-hw_scsi_scsi-disk.c,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Fill in more of SCSI disk block size reports to guest. Allows use of
+sector sizes outside range of 256 to 32768.
+
+--- hw/scsi/scsi-disk.c.orig 2020-08-11 19:17:15.000000000 +0000
++++ hw/scsi/scsi-disk.c
+@@ -1293,9 +1293,9 @@ static int scsi_disk_emulate_mode_sense(
+ p[2] = (nb_sectors >> 8) & 0xff;
+ p[3] = nb_sectors & 0xff;
+ p[4] = 0; /* reserved */
+- p[5] = 0; /* bytes 5-7 are the sector size in bytes */
+- p[6] = s->qdev.blocksize >> 8;
+- p[7] = 0;
++ p[5] = (s->qdev.blocksize >> 16) & 0xff; /* bytes 5-7 are the sector size in bytes */
++ p[6] = (s->qdev.blocksize >> 8) & 0xff;
++ p[7] = s->qdev.blocksize & 0xff;
+ p += 8;
+ }
+
+@@ -1993,10 +1993,10 @@ static int32_t scsi_disk_emulate_command
+ outbuf[1] = (nb_sectors >> 16) & 0xff;
+ outbuf[2] = (nb_sectors >> 8) & 0xff;
+ outbuf[3] = nb_sectors & 0xff;
+- outbuf[4] = 0;
+- outbuf[5] = 0;
+- outbuf[6] = s->qdev.blocksize >> 8;
+- outbuf[7] = 0;
++ outbuf[4] = (s->qdev.blocksize >> 24) & 0xff;;
++ outbuf[5] = (s->qdev.blocksize >> 16) & 0xff;
++ outbuf[6] = (s->qdev.blocksize >> 8) & 0xff;
++ outbuf[7] = s->qdev.blocksize & 0xff;;
+ break;
+ case REQUEST_SENSE:
+ /* Just return "NO SENSE". */
+@@ -2062,10 +2062,10 @@ static int32_t scsi_disk_emulate_command
+ outbuf[5] = (nb_sectors >> 16) & 0xff;
+ outbuf[6] = (nb_sectors >> 8) & 0xff;
+ outbuf[7] = nb_sectors & 0xff;
+- outbuf[8] = 0;
+- outbuf[9] = 0;
+- outbuf[10] = s->qdev.blocksize >> 8;
+- outbuf[11] = 0;
++ outbuf[8] = (s->qdev.blocksize >> 24) & 0xff;
++ outbuf[9] = (s->qdev.blocksize >> 16) & 0xff;
++ outbuf[10] = (s->qdev.blocksize >> 8) & 0xff;
++ outbuf[11] = s->qdev.blocksize & 0xff;
+ outbuf[12] = 0;
+ outbuf[13] = get_physical_block_exp(&s->qdev.conf);
+
Index: pkgsrc/emulators/qemu51/patches/patch-hw_usb_dev-mtp.c
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-hw_usb_dev-mtp.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-hw_usb_dev-mtp.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,27 @@
+$NetBSD: patch-hw_usb_dev-mtp.c,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Support NAME_MAX and compat for O_DIRECTORY.
+
+--- hw/usb/dev-mtp.c.orig 2019-04-23 18:14:46.000000000 +0000
++++ hw/usb/dev-mtp.c
+@@ -26,6 +26,10 @@
+ #include "desc.h"
+ #include "qemu/units.h"
+
++#ifndef NAME_MAX
++#define NAME_MAX 255
++#endif
++
+ /* ----------------------------------------------------------------------- */
+
+ enum mtp_container_type {
+@@ -614,6 +618,9 @@ static void usb_mtp_object_readdir(MTPSt
+ }
+ o->have_children = true;
+
++#ifndef O_DIRECTORY
++#define O_DIRECTORY 0
++#endif
+ fd = open(o->path, O_DIRECTORY | O_CLOEXEC | O_NOFOLLOW);
+ if (fd < 0) {
+ return;
Index: pkgsrc/emulators/qemu51/patches/patch-include_sysemu_hw__accel.h
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-include_sysemu_hw__accel.h:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-include_sysemu_hw__accel.h Sat Feb 20 22:55:19 2021
@@ -0,0 +1,55 @@
+$NetBSD: patch-include_sysemu_hw__accel.h,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Add NVMM support.
+
+--- include/sysemu/hw_accel.h.orig 2020-08-11 19:17:15.000000000 +0000
++++ include/sysemu/hw_accel.h
+@@ -16,6 +16,7 @@
+ #include "sysemu/kvm.h"
+ #include "sysemu/hvf.h"
+ #include "sysemu/whpx.h"
++#include "sysemu/nvmm.h"
+
+ static inline void cpu_synchronize_state(CPUState *cpu)
+ {
+@@ -31,6 +32,9 @@ static inline void cpu_synchronize_state
+ if (whpx_enabled()) {
+ whpx_cpu_synchronize_state(cpu);
+ }
++ if (nvmm_enabled()) {
++ nvmm_cpu_synchronize_state(cpu);
++ }
+ }
+
+ static inline void cpu_synchronize_post_reset(CPUState *cpu)
+@@ -47,6 +51,10 @@ static inline void cpu_synchronize_post_
+ if (whpx_enabled()) {
+ whpx_cpu_synchronize_post_reset(cpu);
+ }
++ if (nvmm_enabled()) {
++ nvmm_cpu_synchronize_post_reset(cpu);
++ }
++
+ }
+
+ static inline void cpu_synchronize_post_init(CPUState *cpu)
+@@ -63,6 +71,9 @@ static inline void cpu_synchronize_post_
+ if (whpx_enabled()) {
+ whpx_cpu_synchronize_post_init(cpu);
+ }
++ if (nvmm_enabled()) {
++ nvmm_cpu_synchronize_post_init(cpu);
++ }
+ }
+
+ static inline void cpu_synchronize_pre_loadvm(CPUState *cpu)
+@@ -79,6 +90,9 @@ static inline void cpu_synchronize_pre_l
+ if (whpx_enabled()) {
+ whpx_cpu_synchronize_pre_loadvm(cpu);
+ }
++ if (nvmm_enabled()) {
++ nvmm_cpu_synchronize_pre_loadvm(cpu);
++ }
+ }
+
+ #endif /* QEMU_HW_ACCEL_H */
Index: pkgsrc/emulators/qemu51/patches/patch-include_sysemu_kvm.h
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-include_sysemu_kvm.h:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-include_sysemu_kvm.h Sat Feb 20 22:55:19 2021
@@ -0,0 +1,23 @@
+$NetBSD: patch-include_sysemu_kvm.h,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Fix debug build on NetBSD (without Linux-KVM).
+
+--- include/sysemu/kvm.h.orig 2019-12-12 18:20:48.000000000 +0000
++++ include/sysemu/kvm.h
+@@ -465,8 +465,16 @@ int kvm_vm_check_extension(KVMState *s,
+ kvm_vcpu_ioctl(cpu, KVM_ENABLE_CAP, &cap); \
+ })
+
++#ifdef CONFIG_KVM
+ uint32_t kvm_arch_get_supported_cpuid(KVMState *env, uint32_t function,
+ uint32_t index, int reg);
++#else
++#define kvm_arch_get_supported_cpuid(a,b,c,d) \
++ ({ \
++ abort(); \
++ 0; \
++ })
++#endif
+ uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index);
+
+
Index: pkgsrc/emulators/qemu51/patches/patch-include_sysemu_nvmm.h
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-include_sysemu_nvmm.h:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-include_sysemu_nvmm.h Sat Feb 20 22:55:19 2021
@@ -0,0 +1,42 @@
+$NetBSD: patch-include_sysemu_nvmm.h,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Add NVMM support.
+
+--- include/sysemu/nvmm.h.orig 2020-02-06 16:25:13.966985106 +0000
++++ include/sysemu/nvmm.h
+@@ -0,0 +1,35 @@
++/*
++ * Copyright (c) 2018-2019 Maxime Villard, All rights reserved.
++ *
++ * NetBSD Virtual Machine Monitor (NVMM) accelerator support.
++ *
++ * This work is licensed under the terms of the GNU GPL, version 2 or later.
++ * See the COPYING file in the top-level directory.
++ */
++
++#ifndef QEMU_NVMM_H
++#define QEMU_NVMM_H
++
++#include "config-host.h"
++#include "qemu-common.h"
++
++int nvmm_init_vcpu(CPUState *);
++int nvmm_vcpu_exec(CPUState *);
++void nvmm_destroy_vcpu(CPUState *);
++
++void nvmm_cpu_synchronize_state(CPUState *);
++void nvmm_cpu_synchronize_post_reset(CPUState *);
++void nvmm_cpu_synchronize_post_init(CPUState *);
++void nvmm_cpu_synchronize_pre_loadvm(CPUState *);
++
++#ifdef CONFIG_NVMM
++
++int nvmm_enabled(void);
++
++#else /* CONFIG_NVMM */
++
++#define nvmm_enabled() (0)
++
++#endif /* CONFIG_NVMM */
++
++#endif /* CONFIG_NVMM */
Index: pkgsrc/emulators/qemu51/patches/patch-net_tap-solaris.c
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-net_tap-solaris.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-net_tap-solaris.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,14 @@
+$NetBSD: patch-net_tap-solaris.c,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Requires qemu-common.h.
+
+--- net/tap-solaris.c.orig 2019-12-12 18:20:48.000000000 +0000
++++ net/tap-solaris.c
+@@ -23,6 +23,7 @@
+ */
+
+ #include "qemu/osdep.h"
++#include "qemu-common.h"
+ #include "qapi/error.h"
+ #include "tap_int.h"
+ #include "qemu/ctype.h"
Index: pkgsrc/emulators/qemu51/patches/patch-qemu-options.hx
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-qemu-options.hx:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-qemu-options.hx Sat Feb 20 22:55:19 2021
@@ -0,0 +1,42 @@
+$NetBSD: patch-qemu-options.hx,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Add NVMM support.
+
+--- qemu-options.hx.orig 2020-04-28 16:49:25.000000000 +0000
++++ qemu-options.hx
+@@ -26,7 +26,7 @@ DEF("machine", HAS_ARG, QEMU_OPTION_mach
+ "-machine [type=]name[,prop[=value][,...]]\n"
+ " selects emulated machine ('-machine help' for list)\n"
+ " property accel=accel1[:accel2[:...]] selects accelerator\n"
+- " supported accelerators are kvm, xen, hax, hvf, whpx or tcg (default: tcg)\n"
++ " supported accelerators are kvm, xen, hax, hvf, nvmm, whpx or tcg (default: tcg)\n"
+ " vmport=on|off|auto controls emulation of vmport (default: auto)\n"
+ " dump-guest-core=on|off include guest memory in a core dump (default=on)\n"
+ " mem-merge=on|off controls memory merge support (default: on)\n"
+@@ -58,7 +58,7 @@ SRST
+
+ ``accel=accels1[:accels2[:...]]``
+ This is used to enable an accelerator. Depending on the target
+- architecture, kvm, xen, hax, hvf, whpx or tcg can be available.
++ architecture, kvm, xen, hax, hvf, nvmm, whpx or tcg can be available.
+ By default, tcg is used. If there is more than one accelerator
+ specified, the next one is used if the previous one fails to
+ initialize.
+@@ -119,7 +119,7 @@ ERST
+
+ DEF("accel", HAS_ARG, QEMU_OPTION_accel,
+ "-accel [accel=]accelerator[,prop[=value][,...]]\n"
+- " select accelerator (kvm, xen, hax, hvf, whpx or tcg; use 'help' for a list)\n"
++ " select accelerator (kvm, xen, hax, hvf, nvmm, whpx or tcg; use 'help' for a list)\n"
+ " igd-passthru=on|off (enable Xen integrated Intel graphics passthrough, default=off)\n"
+ " kernel-irqchip=on|off|split controls accelerated irqchip support (default=on)\n"
+ " kvm-shadow-mem=size of KVM shadow MMU in bytes\n"
+@@ -128,7 +128,7 @@ DEF("accel", HAS_ARG, QEMU_OPTION_accel,
+ SRST
+ ``-accel name[,prop=value[,...]]``
+ This is used to enable an accelerator. Depending on the target
+- architecture, kvm, xen, hax, hvf, whpx or tcg can be available. By
++ architecture, kvm, xen, hax, hvf, nvmm, whpx or tcg can be available. By
+ default, tcg is used. If there is more than one accelerator
+ specified, the next one is used if the previous one fails to
+ initialize.
Index: pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_hwrpb.h
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_hwrpb.h:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_hwrpb.h Sat Feb 20 22:55:19 2021
@@ -0,0 +1,72 @@
+$NetBSD: patch-roms_qemu-palcode_hwrpb.h,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Add definitions for the Console Terminal Block portion of the HWRPB.
+
+--- roms/qemu-palcode/hwrpb.h.orig 2020-10-03 23:04:51.494017689 +0000
++++ roms/qemu-palcode/hwrpb.h 2020-10-03 23:06:34.713833960 +0000
+@@ -146,6 +146,65 @@ struct crb_struct {
+ struct vf_map_struct map[1];
+ };
+
++struct ctb_struct {
++ unsigned long type;
++ unsigned long unit;
++ unsigned long res0;
++ unsigned long len;
++ unsigned long ipl;
++ unsigned long tintr_vec;
++ unsigned long rintr_vec;
++ unsigned long term_type;
++ unsigned long keybd_type;
++ unsigned long keybd_trans;
++ unsigned long keybd_map;
++ unsigned long keybd_state;
++ unsigned long keybd_last;
++ unsigned long font_us;
++ unsigned long font_mcs;
++ unsigned long font_width;
++ unsigned long font_height;
++ unsigned long mon_width;
++ unsigned long mon_height;
++ unsigned long dpi;
++ unsigned long planes;
++ unsigned long cur_width;
++ unsigned long cur_height;
++ unsigned long head_cnt;
++ unsigned long opwindow;
++ unsigned long head_offset;
++ unsigned long putchar;
++ unsigned long io_state;
++ unsigned long listen_state;
++ unsigned long xaddr;
++ unsigned long turboslot;
++ unsigned long server_off;
++ unsigned long line_off;
++ unsigned char csd;
++};
++
++#define CTB_NONE 0x00
++#define CTB_PRINTERPORT 0x02
++#define CTB_GRAPHICS 0x03
++#define CTB_TYPE4 0x04
++
++/*
++ * Format of the Console Terminal Block Type 4 `turboslot' field:
++ *
++ * 63 40 39 32 31 24 23 16 15 8 7 0
++ * | reserved | channel | hose | bus type | bus | slot|
++ */
++#define CTB_TURBOSLOT_CHANNEL(x) (((x) >> 32) & 0xff)
++#define CTB_TURBOSLOT_HOSE(x) (((x) >> 24) & 0xff)
++#define CTB_TURBOSLOT_TYPE(x) (((x) >> 16) & 0xff)
++#define CTB_TURBOSLOT_BUS(x) (((x) >> 8) & 0xff)
++#define CTB_TURBOSLOT_SLOT(x) ((x) & 0xff)
++
++#define CTB_TURBOSLOT_TYPE_TC 0 /* TURBOchannel */
++#define CTB_TURBOSLOT_TYPE_ISA 1 /* ISA */
++#define CTB_TURBOSLOT_TYPE_EISA 2 /* EISA */
++#define CTB_TURBOSLOT_TYPE_PCI 3 /* PCI */
++
+ struct memclust_struct {
+ unsigned long start_pfn;
+ unsigned long numpages;
Index: pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_init.c
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_init.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_init.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,234 @@
+$NetBSD: patch-roms_qemu-palcode_init.c,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+- Don't include cross-host header files.
+- Initialize the HWRPB CPU ID field with the WHAMI of the primary
+ CPU (and not the CPU type) as per the architecture specification.
+- Don't set the "PALcode memory valid" bit in the PCS flags; that field
+ in the HWRPB is not initialized by this PALcode.
+- Provide a Console Terminal Block (CTB) in the HWRPB - NetBSD requires
+ it to find the console device.
+- Define entry point register $a2 as a config word, rather than just a
+ CPU count, and extract the "-nographic" option passed by Qemu, so that
+ the CTB can be initialized properly.
+- Call the SWPPAL with a private argument in $a4, to specify the value of
+ $pv is to be after the SWPPAL has completed.
+- When a secondary CPU starts up, extract a new value for $pv from the
+ HWRPB "CPU restart data" field, and pass that to the SWPPAL operation
+ used to trampiline to into the kernel entry point.
+
+--- roms/qemu-palcode/init.c.orig 2020-10-03 23:12:30.442663290 +0000
++++ roms/qemu-palcode/init.c 2020-10-03 23:12:34.687159989 +0000
+@@ -18,8 +18,6 @@
+ along with this program; see the file COPYING. If not see
+ <http://www.gnu.org/licenses/>. */
+
+-#include <string.h>
+-#include <stddef.h>
+ #include "hwrpb.h"
+ #include "osf.h"
+ #include "ioport.h"
+@@ -38,11 +36,21 @@
+
+ #define HZ 1024
+
++/*
++ * Register a2 contains configuration information from the VM:
++ *
++ * bits 0-5 -- ncpus
++ * bit 6 -- "nographics" option
++ */
++#define CONFIG_NCPUS(x) ((x) & 63)
++#define CONFIG_NOGRAPHICS(x) ((x) & (1ull << 6))
++
+ struct hwrpb_combine {
+ struct hwrpb_struct hwrpb;
+ struct percpu_struct processor[4];
+ struct memdesc_struct md;
+ struct memclust_struct mc[2];
++ struct ctb_struct ctb;
+ struct crb_struct crb;
+ struct procdesc_struct proc_dispatch;
+ struct procdesc_struct proc_fixup;
+@@ -61,6 +69,8 @@ struct hwrpb_combine hwrpb __attribute__
+
+ void *last_alloc;
+ bool have_vga;
++unsigned int pci_vga_bus;
++unsigned int pci_vga_dev;
+
+ static void *
+ alloc (unsigned long size, unsigned long align)
+@@ -138,11 +148,13 @@ init_page_table(void)
+ }
+
+ static void
+-init_hwrpb (unsigned long memsize, unsigned long cpus)
++init_hwrpb (unsigned long memsize, unsigned long config)
+ {
+ unsigned long pal_pages;
+ unsigned long amask;
+ unsigned long i;
++ unsigned long proc_type = EV4_CPU;
++ unsigned long cpus = CONFIG_NCPUS(config);
+
+ hwrpb.hwrpb.phys_addr = PA(&hwrpb);
+
+@@ -164,12 +176,12 @@ init_hwrpb (unsigned long memsize, unsig
+ switch (__builtin_alpha_implver())
+ {
+ case 0: /* EV4 */
+- hwrpb.hwrpb.cpuid = EV4_CPU;
++ proc_type = EV4_CPU;
+ hwrpb.hwrpb.max_asn = 63;
+ break;
+
+ case 1: /* EV5 */
+- hwrpb.hwrpb.cpuid
++ proc_type
+ = ((amask & 0x101) == 0x101 ? PCA56_CPU /* MAX+BWX */
+ : amask & 1 ? EV56_CPU /* BWX */
+ : EV5_CPU);
+@@ -177,11 +189,12 @@ init_hwrpb (unsigned long memsize, unsig
+ break;
+
+ case 2: /* EV6 */
+- hwrpb.hwrpb.cpuid = (amask & 4 ? EV67_CPU : EV6_CPU); /* CIX */
++ proc_type = (amask & 4 ? EV67_CPU : EV6_CPU); /* CIX */
+ hwrpb.hwrpb.max_asn = 255;
+ break;
+ }
+
++ hwrpb.hwrpb.cpuid = 0; /* CPU #0 is the primary */
+ hwrpb.hwrpb.pagesize = PAGE_SIZE;
+ hwrpb.hwrpb.pa_bits = 40;
+ hwrpb.hwrpb.sys_type = SYS_TYPE;
+@@ -189,9 +202,20 @@ init_hwrpb (unsigned long memsize, unsig
+ hwrpb.hwrpb.sys_revision = SYS_REVISION;
+ for (i = 0; i < cpus; ++i)
+ {
+- /* ??? Look up these bits. Snagging the value examined by the kernel. */
+- hwrpb.processor[i].flags = 0x1cc;
+- hwrpb.processor[i].type = hwrpb.hwrpb.cpuid;
++ /*
++ * original value was 0x1cc ==
++ * PALcode loaded (0x100)
++ * PALcode memory valid (0x080)
++ * PALcode valid (0x040)
++ * processor present (0x008)
++ * processor available (0x004)
++ *
++ * Don't set PALcode memory valid -- we don't initialize those PCS
++ * fields!
++ */
++ hwrpb.processor[i].flags = 0x14c;
++ hwrpb.processor[i].type = proc_type;
++ /* XXX hwrpb.processor[i].pal_revision */
+ }
+
+ hwrpb.hwrpb.intr_freq = HZ * 4096;
+@@ -213,6 +237,21 @@ init_hwrpb (unsigned long memsize, unsig
+ hwrpb.mc[1].start_pfn = pal_pages;
+ hwrpb.mc[1].numpages = (memsize >> PAGE_SHIFT) - pal_pages;
+
++ hwrpb.hwrpb.ctbt_offset = offsetof(struct hwrpb_combine, ctb);
++ hwrpb.hwrpb.ctb_size = sizeof(hwrpb.ctb);
++ if (have_vga && !CONFIG_NOGRAPHICS(config))
++ {
++ printf("CTB: GRAPHICS PCI BUS %d DEV %d\r\n", pci_vga_bus, pci_vga_dev);
++ hwrpb.ctb.term_type = CTB_GRAPHICS;
++ hwrpb.ctb.turboslot = (CTB_TURBOSLOT_TYPE_PCI << 16) |
++ (pci_vga_bus << 8) | pci_vga_dev;
++ }
++ else
++ {
++ printf("CTB: PRINTERPORT\r\n");
++ hwrpb.ctb.term_type = CTB_PRINTERPORT;
++ }
++
+ hwrpb.hwrpb.crb_offset = offsetof(struct hwrpb_combine, crb);
+ hwrpb.crb.dispatch_va = &hwrpb.proc_dispatch;
+ hwrpb.crb.dispatch_pa = PA(&hwrpb.proc_dispatch);
+@@ -260,7 +299,7 @@ init_i8259 (void)
+ outb(0x01, PORT_PIC1_DATA); /* ICW4 */
+
+ /* Initialize level triggers. The CY82C693UB that's on real alpha
+- hardware doesn't have this; this is a PIIX extension. However,
++ hardware controls these differently; we assume a PIIX here. However,
+ QEMU doesn't implement regular level triggers. */
+ outb(0xff, PORT_PIC2_ELCR);
+ outb(0xff, PORT_PIC1_ELCR);
+@@ -275,32 +314,37 @@ init_i8259 (void)
+ }
+
+ static void __attribute__((noreturn))
+-swppal(void *entry, void *pcb)
++swppal(void *entry, void *pcb, unsigned long vptptr, unsigned long pv)
+ {
+ register int variant __asm__("$16") = 2; /* OSF/1 PALcode */
+ register void *pc __asm__("$17") = entry;
+ register unsigned long pa_pcb __asm__("$18") = PA(pcb);
+- register unsigned long vptptr __asm__("$19") = VPTPTR;
++ register unsigned long newvptptr __asm__("$19") = vptptr;
++ register unsigned long newpv __asm__("$20") = pv;
+
+- asm("call_pal 0x0a" : : "r"(variant), "r"(pc), "r"(pa_pcb), "r"(vptptr));
++ asm("call_pal 0x0a" : :
++ "r"(variant), "r"(pc), "r"(pa_pcb), "r"(newvptptr), "r"(newpv));
+ __builtin_unreachable ();
+ }
+
+ void
+-do_start(unsigned long memsize, void (*kernel_entry)(void), unsigned long cpus)
++do_start(unsigned long memsize, void (*kernel_entry)(void),
++ unsigned long config)
+ {
+ last_alloc = _end;
+
+ init_page_table();
+- init_hwrpb(memsize, cpus);
+ init_pcb();
+ init_i8259();
+ uart_init();
+ ps2port_setup();
+ pci_setup();
+ vgahw_init();
++ init_hwrpb(memsize, config);
+
+- swppal(kernel_entry ? kernel_entry : do_console, &pcb);
++ void *new_pc = kernel_entry ? kernel_entry : do_console;
++
++ swppal(new_pc, &pcb, VPTPTR, (unsigned long)new_pc);
+ }
+
+ void
+@@ -315,14 +359,16 @@ do_start_wait(unsigned long cpuid)
+ {
+ /* ??? The only message I know of is "START\r\n".
+ I can't be bothered to verify more than 4 characters. */
+- /* ??? The Linux kernel fills in, but does not require,
+- CPU_restart_data. It just sets that to the same address
+- as CPU_restart itself. Our swppal *does* put the PC into
+- $26 and $27, the latter of which the kernel does rely upon. */
++
++ /* Use use a private extension to SWPPAL to get the
++ CPU_restart_data into $27. Linux fills it in, but does
++ not require it. Other operating system, however,s do use
++ CPU_restart_data as part of secondary CPU start-up. */
+
+ unsigned int len = hwrpb.processor[cpuid].ipc_buffer[0];
+ unsigned int msg = hwrpb.processor[cpuid].ipc_buffer[1];
+ void *CPU_restart = hwrpb.hwrpb.CPU_restart;
++ unsigned long CPU_restart_data = hwrpb.hwrpb.CPU_restart_data;
+ __sync_synchronize();
+ hwrpb.hwrpb.rxrdy = 0;
+
+@@ -330,7 +376,8 @@ do_start_wait(unsigned long cpuid)
+ {
+ /* Set bootstrap in progress */
+ hwrpb.processor[cpuid].flags |= 1;
+- swppal(CPU_restart, hwrpb.processor[cpuid].hwpcb);
++ swppal(CPU_restart, hwrpb.processor[cpuid].hwpcb,
++ hwrpb.hwrpb.vptb, CPU_restart_data);
+ }
+ }
+ }
Index: pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_memcpy.c
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_memcpy.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_memcpy.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,15 @@
+$NetBSD: patch-roms_qemu-palcode_memcpy.c,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Include local header file for prototypes.
+
+--- roms/qemu-palcode/memcpy.c.orig 2020-10-04 16:22:55.342263484 +0000
++++ roms/qemu-palcode/memcpy.c 2020-10-04 16:23:41.685256308 +0000
+@@ -8,7 +8,7 @@
+ * This is a reasonably optimized memcpy() routine.
+ */
+
+-#include <string.h>
++#include "protos.h"
+
+ /*
+ * Note that the C code is written to be optimized into good assembly. However,
Index: pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_memset.c
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_memset.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_memset.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,15 @@
+$NetBSD: patch-roms_qemu-palcode_memset.c,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Include local header file for prototypes.
+
+--- roms/qemu-palcode/memset.c.orig 2020-10-04 16:26:11.159949099 +0000
++++ roms/qemu-palcode/memset.c 2020-10-04 16:29:02.795766148 +0000
+@@ -19,7 +19,7 @@
+ <http://www.gnu.org/licenses/>. */
+
+
+-#include <string.h>
++#include "protos.h"
+
+ void *memset(void *optr, int ival, unsigned long size)
+ {
Index: pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_pal.S
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_pal.S:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_pal.S Sat Feb 20 22:55:19 2021
@@ -0,0 +1,53 @@
+$NetBSD: patch-roms_qemu-palcode_pal.S,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+In SWPPAL, allow an additional, non-architected argument for the
+switch to OSF/1 PALcode. This extra argument specifies the desired
+value of $pv after SWPPAL has completed, and is for internal PALcode
+use only and is needed for secondary CPU spin-up. This is allowed
+because per the architecure specification, all registers other than
+$sp and $v0 are UNPREDICTABLE after SWPPAL, and this PALcode's use
+of SWPPAL for secondary CPU spin-up is an implementation detail.
+This PALcode was already relying on this UNPREDICTABLE behavior for
+its own purposes; this change merely gives control of this behavior
+to internal SWPPAL callers.
+
+--- roms/qemu-palcode/pal.S.orig 2020-10-04 16:32:44.901663159 +0000
++++ roms/qemu-palcode/pal.S 2020-10-04 16:31:30.356343608 +0000
+@@ -566,6 +566,8 @@ ENDFN CallPal_Cserve_Cont
+ * r17 (a1) = New PC
+ * r18 (a2) = New PCB
+ * r19 (a3) = New VptPtr
++ * r20 (a4) = New Procedure Value (to place into $27)
++ * (Non-standard; See note below.)
+ *
+ * OUTPUT PARAMETERS:
+ *
+@@ -574,11 +576,15 @@ ENDFN CallPal_Cserve_Cont
+ * 1 - Unknown PALcode variant
+ * 2 - Known PALcode variant, but PALcode not loaded
+ *
+- * r26 (ra) = r27 (pv) = New PC
+- * Note that this is non-architected, but is relied on by
++ * r26 (ra) = New PC
++ * r27 (pv) = From $20
++ * Note that this is non-architected, but is relied upon by
+ * the usage of SwpPal within our own console code in order
+- * to simplify its use within C code.
+- *
++ * to simplify its use within C code. We can get away with
++ * the extra non-standard argument (in $20) because as
++ * architected, all registers except SP and R0 are
++ * UNPREDICTABLE; therefore private internal usage is
++ * fine.
+ */
+ ORG_CALL_PAL_PRIV(0x0A)
+ CallPal_SwpPal:
+@@ -624,7 +630,7 @@ CallPal_SwpPal_Cont:
+ mtpr $31, qemu_tbia // Flush TLB for new PTBR
+
+ mov a1, $26
+- mov a1, $27
++ mov a4, $27
+ hw_ret (a1)
+ ENDFN CallPal_SwpPal_Cont
+ .previous
Index: pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_pci.c
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_pci.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_pci.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,78 @@
+$NetBSD: patch-roms_qemu-palcode_pci.c,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+- Move PCI_DEVFN(), PCI_BUS(), PCI_SLOT(), and PCI_FUNC() to pci.h.
+- Improve debug/info messages.
+- Only program a BAR as a 64-bit MEM BAR if it really is a 64-bit MEM BAR.
+ Fixes an issue with the CMD646 IDE controller under NetBSD.
+- Use system-specific information to program the interrupt line register
+ with the interrupt mappings, which is what the SRM console does on real
+ hardware; some operating systems (e.g. NetBSD) use this information
+ rather than having interrupt mapping tables for every possible system
+ variation.
+
+--- roms/qemu-palcode/pci.c.orig 2020-10-04 16:41:22.923562768 +0000
++++ roms/qemu-palcode/pci.c 2020-10-04 16:41:58.183954279 +0000
+@@ -29,12 +29,9 @@
+ #include "protos.h"
+ #include "pci.h"
+ #include "pci_regs.h"
++#include SYSTEM_H
+
+
+-#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
+-#define PCI_BUS(devfn) ((devfn) >> 8)
+-#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
+-#define PCI_FUNC(devfn) ((devfn) & 0x07)
+ #define PCI_SLOT_MAX 32
+ #define PCI_FUNC_MAX 8
+ #define PCI_REGION_ROM 6
+@@ -88,7 +85,7 @@ pci_setup_device(int bdf, uint32_t *p_io
+ device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
+ class_id = pci_config_readw(bdf, PCI_CLASS_DEVICE);
+
+- printf("PCI: %02x:%02x:%x class %04x id %04x:%04x\r\n",
++ printf("PCI: %d:%d:%d class %04x id %04x:%04x\r\n",
+ PCI_BUS(bdf), PCI_SLOT(bdf), PCI_FUNC(bdf),
+ class_id, vendor_id, device_id);
+
+@@ -122,9 +119,11 @@ pci_setup_device(int bdf, uint32_t *p_io
+ *p_base = addr + size;
+ pci_config_writel(bdf, ofs, addr);
+
+- printf("PCI: region %d: %08x\r\n", region, addr);
++ printf("PCI: region %d (BAR %02x): %08x\r\n",
++ region, ofs, addr);
+
+- if ((val & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
++ if ((old & PCI_BASE_ADDRESS_SPACE_IO) == 0 &&
++ (old & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
+ == PCI_BASE_ADDRESS_MEM_TYPE_64)
+ {
+ pci_config_writel(bdf, ofs + 4, 0);
+@@ -135,7 +134,25 @@ pci_setup_device(int bdf, uint32_t *p_io
+
+ pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
+
+- /* Map the interrupt. */
++ /* Map the interrupt and program the IRQ into the line register.
++ Some operating systems rely on the Console providing this information
++ in order to avoid having mapping tables for every possible system
++ variation. */
++
++ const uint8_t pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
++ const uint8_t slot = PCI_SLOT(bdf);
++ const int irq = MAP_PCI_INTERRUPT(slot, pin, class_id);
++
++ if (irq == -1)
++ {
++ /* No interrupt mapping. */
++ pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 0xff);
++ }
++ else
++ {
++ printf("PCI: intr pin %d -> irq %d\r\n", pin, irq);
++ pci_config_writeb(bdf, PCI_INTERRUPT_LINE, irq);
++ }
+ }
+
+ void
Index: pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_pci.h
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_pci.h:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_pci.h Sat Feb 20 22:55:19 2021
@@ -0,0 +1,18 @@
+$NetBSD: patch-roms_qemu-palcode_pci.h,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Move PCI_DEVFN(), PCI_BUS(), PCI_SLOT(), and PCI_FUNC() to pci.h.
+
+--- roms/qemu-palcode/pci.h.orig 2020-10-04 16:48:50.267686138 +0000
++++ roms/qemu-palcode/pci.h 2020-10-04 16:49:11.064722703 +0000
+@@ -60,6 +60,11 @@ extern void pci_config_maskw(int bdf, in
+
+ extern int pci_next(int bdf, int *pmax);
+
++#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
++#define PCI_BUS(devfn) ((devfn) >> 8)
++#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
++#define PCI_FUNC(devfn) ((devfn) & 0x07)
++
+ #define foreachpci(BDF, MAX) \
+ for (MAX = 0x0100, BDF = pci_next(0, &MAX); \
+ BDF >= 0; \
Index: pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_printf.c
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_printf.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_printf.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,31 @@
+$NetBSD: patch-roms_qemu-palcode_printf.c,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+- Include local header file for prototypes.
+- Add puts(), which the compiler may emit a call to if the string passed
+ to printf has no format specifiers.
+
+--- roms/qemu-palcode/printf.c.orig 2020-10-04 17:01:51.396706889 +0000
++++ roms/qemu-palcode/printf.c 2020-10-04 17:02:27.588036847 +0000
+@@ -18,10 +18,8 @@
+ along with this program; see the file COPYING. If not see
+ <http://www.gnu.org/licenses/>. */
+
+-#include <stdarg.h>
+-#include <stdbool.h>
+-#include <string.h>
+ #include "console.h"
++#include "protos.h"
+
+ static int print_buf_pad(char *buf, int buflen, char *p, int width, int pad)
+ {
+@@ -201,3 +199,10 @@ int printf(const char *fmt, ...)
+ va_end(args);
+ return r;
+ }
++
++int puts(const char *s)
++{
++ int len = strlen(s);
++ crb_puts(0, s, len);
++ return len;
++}
Index: pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_protos.h
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_protos.h:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_protos.h Sat Feb 20 22:55:19 2021
@@ -0,0 +1,66 @@
+$NetBSD: patch-roms_qemu-palcode_protos.h,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+- Don't include system headers. Instead, provide standalone definitions
+ and declarations of types needed and functions used by the PALcode that
+ are compatible with the standard Alpha / GCC ABI.
+- Add pci_vga_bus and pci_vga_dev globals so that the HWRPB CTB can
+ correctly reflect the location of the a graphics console.
+
+--- roms/qemu-palcode/protos.h.orig 2020-10-04 17:05:39.239008051 +0000
++++ roms/qemu-palcode/protos.h 2020-10-04 17:06:01.772319919 +0000
+@@ -21,11 +21,33 @@
+ #ifndef PROTOS_H
+ #define PROTOS_H 1
+
+-#include <stdint.h>
+-#include <stdbool.h>
+-#include <stddef.h>
+-#include <string.h>
+-
++/*
++ * Stand-alone definitions for various types, compatible with
++ * the Alpha Linux ABI and GCC. This eliminates dependencies
++ * on external headers.
++ */
++typedef unsigned char uint8_t;
++typedef unsigned short uint16_t;
++typedef unsigned int uint32_t;
++typedef unsigned long uint64_t;
++typedef unsigned long size_t;
++
++#define bool _Bool
++#define true 1
++#define false 0
++
++#define offsetof(type, member) __builtin_offsetof(type, member)
++
++typedef __builtin_va_list va_list;
++#define va_start(ap, last) __builtin_va_start((ap), (last))
++#define va_arg __builtin_va_arg
++#define va_end(ap) __builtin_va_end(ap)
++
++#define NULL ((void *)0)
++
++extern void *memset(void *, int, size_t);
++extern void *memcpy(void *, const void *, size_t);
++extern size_t strlen(const char *);
+
+ /*
+ * Call_Pal functions.
+@@ -202,6 +224,8 @@ extern unsigned long crb_fixup(unsigned
+ */
+
+ extern bool have_vga;
++extern unsigned int pci_vga_bus;
++extern unsigned int pci_vga_dev;
+
+ extern void do_console(void);
+ extern void entInt(void);
+@@ -211,6 +235,7 @@ extern void entInt(void);
+ */
+
+ extern int printf(const char *, ...);
++extern int puts(const char *);
+ extern void ndelay(unsigned long nsec);
+
+ static inline void udelay(unsigned long msec)
Index: pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_sys-clipper.h
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_sys-clipper.h:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_sys-clipper.h Sat Feb 20 22:55:19 2021
@@ -0,0 +1,38 @@
+$NetBSD: patch-roms_qemu-palcode_sys-clipper.h,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Povide PCI device interrupt mapping information.
+
+--- roms/qemu-palcode/sys-clipper.h.orig 2020-10-04 17:10:06.597880613 +0000
++++ roms/qemu-palcode/sys-clipper.h 2020-10-04 17:10:33.149119398 +0000
+@@ -27,4 +27,31 @@
+ #define SYS_VARIATION (5 << 10)
+ #define SYS_REVISION 0
+
++#ifndef __ASSEMBLER__
++
++#define MAP_PCI_INTERRUPT(SLOT, PIN, CLASS_ID) \
++({ \
++ int IRQ; \
++ \
++ if (CLASS_ID == 0x0601) \
++ { \
++ /* PCI-ISA bridge is hard-wired to IRQ 55 on real hardware, \
++ and comes in at a different SCB vector; force the line \
++ register to -1. */ \
++ IRQ = -1; \
++ } \
++ else if (PIN >= 1 && PIN <= 4) \
++ { \
++ /* See hw/alpha/dp264.c:clipper_pci_map_irq() */ \
++ IRQ = (SLOT + 1) * 4 + (PIN - 1); \
++ } \
++ else \
++ { \
++ IRQ = -1; \
++ } \
++ IRQ; \
++})
++
++#endif /* ! __ASSEMBLER__ */
++
+ #endif
Index: pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_vgaio.c
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_vgaio.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-roms_qemu-palcode_vgaio.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,16 @@
+$NetBSD: patch-roms_qemu-palcode_vgaio.c,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Add pci_vga_bus and pci_vga_dev globals so that the HWRPB CTB can
+correctly reflect the location of the a graphics console.
+
+--- roms/qemu-palcode/vgaio.c.orig 2020-10-04 17:12:53.089367837 +0000
++++ roms/qemu-palcode/vgaio.c 2020-10-04 17:13:21.240322169 +0000
+@@ -570,6 +570,8 @@ vgahw_init(void)
+
+ found:
+ have_vga = 1;
++ pci_vga_bus = PCI_BUS(bdf);
++ pci_vga_dev = PCI_SLOT(bdf);
+
+ vmode_g = find_vga_entry(3);
+
Index: pkgsrc/emulators/qemu51/patches/patch-roms_u-boot-sam460ex_Makefile
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-roms_u-boot-sam460ex_Makefile:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-roms_u-boot-sam460ex_Makefile Sat Feb 20 22:55:19 2021
@@ -0,0 +1,32 @@
+$NetBSD: patch-roms_u-boot-sam460ex_Makefile,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Shell compatibility
+
+--- roms/u-boot-sam460ex/Makefile.orig 2019-12-12 18:22:51.000000000 +0000
++++ roms/u-boot-sam460ex/Makefile
+@@ -2189,10 +2189,10 @@ M5475GFE_config : unconfig
+ if [ "$${CODE}" != "0" ] ; then \
+ echo "#define CONFIG_SYS_NOR1SZ $${CODE}" >> $(obj)include/config.h ; \
+ fi; \
+- if [ "$${VID}" == "1" ] ; then \
++ if [ "$${VID}" = "1" ] ; then \
+ echo "#define CONFIG_SYS_VIDEO" >> $(obj)include/config.h ; \
+ fi; \
+- if [ "$${USB}" == "1" ] ; then \
++ if [ "$${USB}" = "1" ] ; then \
+ echo "#define CONFIG_SYS_USBCTRL" >> $(obj)include/config.h ; \
+ fi
+ @$(MKCONFIG) -a M5475EVB m68k mcf547x_8x m547xevb freescale
+@@ -2224,10 +2224,10 @@ M5485HFE_config : unconfig
+ if [ "$${CODE}" != "0" ] ; then \
+ echo "#define CONFIG_SYS_NOR1SZ $${CODE}" >> $(obj)include/config.h ; \
+ fi; \
+- if [ "$${VID}" == "1" ] ; then \
++ if [ "$${VID}" = "1" ] ; then \
+ echo "#define CONFIG_SYS_VIDEO" >> $(obj)include/config.h ; \
+ fi; \
+- if [ "$${USB}" == "1" ] ; then \
++ if [ "$${USB}" = "1" ] ; then \
+ echo "#define CONFIG_SYS_USBCTRL" >> $(obj)include/config.h ; \
+ fi
+ @$(MKCONFIG) -a M5485EVB m68k mcf547x_8x m548xevb freescale
Index: pkgsrc/emulators/qemu51/patches/patch-roms_u-boot_tools_imx8m__image.sh
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-roms_u-boot_tools_imx8m__image.sh:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-roms_u-boot_tools_imx8m__image.sh Sat Feb 20 22:55:19 2021
@@ -0,0 +1,24 @@
+$NetBSD: patch-roms_u-boot_tools_imx8m__image.sh,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+* Improve POSIX shell portability
+
+--- roms/u-boot/tools/imx8m_image.sh.orig 2019-04-23 18:16:46.000000000 +0000
++++ roms/u-boot/tools/imx8m_image.sh
+@@ -12,7 +12,7 @@ blobs=`awk '/^SIGNED_HDMI/ {print $2} /^
+ for f in $blobs; do
+ tmp=$srctree/$f
+
+- if [ $f == "spl/u-boot-spl-ddr.bin" ] || [ $f == "u-boot.itb" ]; then
++ if [ $f = "spl/u-boot-spl-ddr.bin" ] || [ $f = "u-boot.itb" ]; then
+ continue
+ fi
+
+@@ -28,7 +28,7 @@ for f in $blobs; do
+ sed -in "s;$f;$tmp;" $file
+ done
+
+-if [ $post_process == 1 ]; then
++if [ $post_process = 1 ]; then
+ if [ -f $srctree/lpddr4_pmu_train_1d_imem.bin ]; then
+ objcopy -I binary -O binary --pad-to 0x8000 --gap-fill=0x0 $srctree/lpddr4_pmu_train_1d_imem.bin lpddr4_pmu_train_1d_imem_pad.bin
+ objcopy -I binary -O binary --pad-to 0x4000 --gap-fill=0x0 $srctree/lpddr4_pmu_train_1d_dmem.bin lpddr4_pmu_train_1d_dmem_pad.bin
Index: pkgsrc/emulators/qemu51/patches/patch-softmmu_cpus.c
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-softmmu_cpus.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-softmmu_cpus.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,92 @@
+$NetBSD: patch-softmmu_cpus.c,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Add NVMM support.
+
+--- softmmu/cpus.c.orig 2019-12-12 18:20:47.000000000 +0000
++++ softmmu/cpus.c
+@@ -42,6 +42,7 @@
+ #include "sysemu/hax.h"
+ #include "sysemu/hvf.h"
+ #include "sysemu/whpx.h"
++#include "sysemu/nvmm.h"
+ #include "exec/exec-all.h"
+
+ #include "qemu/thread.h"
+@@ -1738,6 +1739,48 @@ static void *qemu_whpx_cpu_thread_fn(voi
+ return NULL;
+ }
+
++static void *qemu_nvmm_cpu_thread_fn(void *arg)
++{
++ CPUState *cpu = arg;
++ int r;
++
++ assert(nvmm_enabled());
++
++ rcu_register_thread();
++
++ qemu_mutex_lock_iothread();
++ qemu_thread_get_self(cpu->thread);
++ cpu->thread_id = qemu_get_thread_id();
++ current_cpu = cpu;
++
++ r = nvmm_init_vcpu(cpu);
++ if (r < 0) {
++ fprintf(stderr, "nvmm_init_vcpu failed: %s\n", strerror(-r));
++ exit(1);
++ }
++
++ /* signal CPU creation */
++ cpu->created = true;
++ qemu_cond_signal(&qemu_cpu_cond);
++
++ do {
++ if (cpu_can_run(cpu)) {
++ r = nvmm_vcpu_exec(cpu);
++ if (r == EXCP_DEBUG) {
++ cpu_handle_guest_debug(cpu);
++ }
++ }
++ qemu_wait_io_event(cpu);
++ } while (!cpu->unplug || cpu_can_run(cpu));
++
++ nvmm_destroy_vcpu(cpu);
++ cpu->created = false;
++ qemu_cond_signal(&qemu_cpu_cond);
++ qemu_mutex_unlock_iothread();
++ rcu_unregister_thread();
++ return NULL;
++}
++
+ #ifdef _WIN32
+ static void CALLBACK dummy_apc_func(ULONG_PTR unused)
+ {
+@@ -2101,6 +2144,19 @@ static void qemu_whpx_start_vcpu(CPUStat
+ #endif
+ }
+
++static void qemu_nvmm_start_vcpu(CPUState *cpu)
++{
++ char thread_name[VCPU_THREAD_NAME_SIZE];
++
++ cpu->thread = g_malloc0(sizeof(QemuThread));
++ cpu->halt_cond = g_malloc0(sizeof(QemuCond));
++ qemu_cond_init(cpu->halt_cond);
++ snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "CPU %d/NVMM",
++ cpu->cpu_index);
++ qemu_thread_create(cpu->thread, thread_name, qemu_nvmm_cpu_thread_fn,
++ cpu, QEMU_THREAD_JOINABLE);
++}
++
+ static void qemu_dummy_start_vcpu(CPUState *cpu)
+ {
+ char thread_name[VCPU_THREAD_NAME_SIZE];
+@@ -2141,6 +2197,8 @@ void qemu_init_vcpu(CPUState *cpu)
+ qemu_tcg_init_vcpu(cpu);
+ } else if (whpx_enabled()) {
+ qemu_whpx_start_vcpu(cpu);
++ } else if (nvmm_enabled()) {
++ qemu_nvmm_start_vcpu(cpu);
+ } else {
+ qemu_dummy_start_vcpu(cpu);
+ }
Index: pkgsrc/emulators/qemu51/patches/patch-target_i386_Makefile.objs
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-target_i386_Makefile.objs:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-target_i386_Makefile.objs Sat Feb 20 22:55:19 2021
@@ -0,0 +1,14 @@
+$NetBSD: patch-target_i386_Makefile.objs,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Add NVMM support.
+
+--- target/i386/Makefile.objs.orig 2019-12-12 18:20:48.000000000 +0000
++++ target/i386/Makefile.objs
+@@ -17,6 +17,7 @@ obj-$(CONFIG_HAX) += hax-all.o hax-mem.o
+ endif
+ obj-$(CONFIG_HVF) += hvf/
+ obj-$(CONFIG_WHPX) += whpx-all.o
++obj-$(CONFIG_NVMM) += nvmm-all.o
+ endif
+ obj-$(CONFIG_SEV) += sev.o
+ obj-$(call lnot,$(CONFIG_SEV)) += sev-stub.o
Index: pkgsrc/emulators/qemu51/patches/patch-target_i386_helper.c
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-target_i386_helper.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-target_i386_helper.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,15 @@
+$NetBSD: patch-target_i386_helper.c,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Add NVMM support.
+
+--- target/i386/helper.c.orig 2019-12-12 18:20:48.000000000 +0000
++++ target/i386/helper.c
+@@ -981,7 +981,7 @@ void cpu_report_tpr_access(CPUX86State *
+ X86CPU *cpu = env_archcpu(env);
+ CPUState *cs = env_cpu(env);
+
+- if (kvm_enabled() || whpx_enabled()) {
++ if (kvm_enabled() || whpx_enabled() || nvmm_enabled()) {
+ env->tpr_access_type = access;
+
+ cpu_interrupt(cs, CPU_INTERRUPT_TPR);
Index: pkgsrc/emulators/qemu51/patches/patch-target_i386_kvm-stub.c
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-target_i386_kvm-stub.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-target_i386_kvm-stub.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,23 @@
+$NetBSD: patch-target_i386_kvm-stub.c,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Fix debug build on NetBSD (without Linux-KVM).
+
+--- target/i386/kvm-stub.c.orig 2019-02-02 13:12:09.564671574 +0000
++++ target/i386/kvm-stub.c
+@@ -29,16 +29,6 @@ bool kvm_enable_x2apic(void)
+ {
+ return false;
+ }
+-
+-/* This function is only called inside conditionals which we
+- * rely on the compiler to optimize out when CONFIG_KVM is not
+- * defined.
+- */
+-uint32_t kvm_arch_get_supported_cpuid(KVMState *env, uint32_t function,
+- uint32_t index, int reg)
+-{
+- abort();
+-}
+ #endif
+
+ bool kvm_hv_vpindex_settable(void)
Index: pkgsrc/emulators/qemu51/patches/patch-target_i386_nvmm-all.c
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-target_i386_nvmm-all.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-target_i386_nvmm-all.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,1233 @@
+$NetBSD: patch-target_i386_nvmm-all.c,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Add NVMM support.
+
+--- target/i386/nvmm-all.c.orig 2020-02-06 23:03:06.140694264 +0000
++++ target/i386/nvmm-all.c
+@@ -0,0 +1,1226 @@
++/*
++ * Copyright (c) 2018-2019 Maxime Villard, All rights reserved.
++ *
++ * NetBSD Virtual Machine Monitor (NVMM) accelerator for QEMU.
++ *
++ * This work is licensed under the terms of the GNU GPL, version 2 or later.
++ * See the COPYING file in the top-level directory.
++ */
++
++#include "qemu/osdep.h"
++#include "cpu.h"
++#include "exec/address-spaces.h"
++#include "exec/ioport.h"
++#include "qemu-common.h"
++#include "strings.h"
++#include "sysemu/accel.h"
++#include "sysemu/nvmm.h"
++#include "sysemu/runstate.h"
++#include "sysemu/sysemu.h"
++#include "sysemu/cpus.h"
++#include "qemu/main-loop.h"
++#include "qemu/error-report.h"
++#include "qemu/queue.h"
++#include "qapi/error.h"
++#include "migration/blocker.h"
++
++#include <nvmm.h>
++
++struct qemu_vcpu {
++ struct nvmm_vcpu vcpu;
++ uint8_t tpr;
++ bool stop;
++
++ /* Window-exiting for INTs/NMIs. */
++ bool int_window_exit;
++ bool nmi_window_exit;
++
++ /* The guest is in an interrupt shadow (POP SS, etc). */
++ bool int_shadow;
++};
++
++struct qemu_machine {
++ struct nvmm_capability cap;
++ struct nvmm_machine mach;
++};
++
++/* -------------------------------------------------------------------------- */
++
++static bool nvmm_allowed;
++static struct qemu_machine qemu_mach;
++
++static struct qemu_vcpu *
++get_qemu_vcpu(CPUState *cpu)
++{
++ return (struct qemu_vcpu *)cpu->hax_vcpu;
++}
++
++static struct nvmm_machine *
++get_nvmm_mach(void)
++{
++ return &qemu_mach.mach;
++}
++
++/* -------------------------------------------------------------------------- */
++
++static void
++nvmm_set_segment(struct nvmm_x64_state_seg *nseg, const SegmentCache *qseg)
++{
++ uint32_t attrib = qseg->flags;
++
++ nseg->selector = qseg->selector;
++ nseg->limit = qseg->limit;
++ nseg->base = qseg->base;
++ nseg->attrib.type = __SHIFTOUT(attrib, DESC_TYPE_MASK);
++ nseg->attrib.s = __SHIFTOUT(attrib, DESC_S_MASK);
++ nseg->attrib.dpl = __SHIFTOUT(attrib, DESC_DPL_MASK);
++ nseg->attrib.p = __SHIFTOUT(attrib, DESC_P_MASK);
++ nseg->attrib.avl = __SHIFTOUT(attrib, DESC_AVL_MASK);
++ nseg->attrib.l = __SHIFTOUT(attrib, DESC_L_MASK);
++ nseg->attrib.def = __SHIFTOUT(attrib, DESC_B_MASK);
++ nseg->attrib.g = __SHIFTOUT(attrib, DESC_G_MASK);
++}
++
++static void
++nvmm_set_registers(CPUState *cpu)
++{
++ struct CPUX86State *env = (CPUArchState *)cpu->env_ptr;
++ struct nvmm_machine *mach = get_nvmm_mach();
++ struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu);
++ struct nvmm_vcpu *vcpu = &qcpu->vcpu;
++ struct nvmm_x64_state *state = vcpu->state;
++ uint64_t bitmap;
++ size_t i;
++ int ret;
++
++ assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
++
++ /* GPRs. */
++ state->gprs[NVMM_X64_GPR_RAX] = env->regs[R_EAX];
++ state->gprs[NVMM_X64_GPR_RCX] = env->regs[R_ECX];
++ state->gprs[NVMM_X64_GPR_RDX] = env->regs[R_EDX];
++ state->gprs[NVMM_X64_GPR_RBX] = env->regs[R_EBX];
++ state->gprs[NVMM_X64_GPR_RSP] = env->regs[R_ESP];
++ state->gprs[NVMM_X64_GPR_RBP] = env->regs[R_EBP];
++ state->gprs[NVMM_X64_GPR_RSI] = env->regs[R_ESI];
++ state->gprs[NVMM_X64_GPR_RDI] = env->regs[R_EDI];
++#ifdef TARGET_X86_64
++ state->gprs[NVMM_X64_GPR_R8] = env->regs[R_R8];
++ state->gprs[NVMM_X64_GPR_R9] = env->regs[R_R9];
++ state->gprs[NVMM_X64_GPR_R10] = env->regs[R_R10];
++ state->gprs[NVMM_X64_GPR_R11] = env->regs[R_R11];
++ state->gprs[NVMM_X64_GPR_R12] = env->regs[R_R12];
++ state->gprs[NVMM_X64_GPR_R13] = env->regs[R_R13];
++ state->gprs[NVMM_X64_GPR_R14] = env->regs[R_R14];
++ state->gprs[NVMM_X64_GPR_R15] = env->regs[R_R15];
++#endif
++
++ /* RIP and RFLAGS. */
++ state->gprs[NVMM_X64_GPR_RIP] = env->eip;
++ state->gprs[NVMM_X64_GPR_RFLAGS] = env->eflags;
++
++ /* Segments. */
++ nvmm_set_segment(&state->segs[NVMM_X64_SEG_CS], &env->segs[R_CS]);
++ nvmm_set_segment(&state->segs[NVMM_X64_SEG_DS], &env->segs[R_DS]);
++ nvmm_set_segment(&state->segs[NVMM_X64_SEG_ES], &env->segs[R_ES]);
++ nvmm_set_segment(&state->segs[NVMM_X64_SEG_FS], &env->segs[R_FS]);
++ nvmm_set_segment(&state->segs[NVMM_X64_SEG_GS], &env->segs[R_GS]);
++ nvmm_set_segment(&state->segs[NVMM_X64_SEG_SS], &env->segs[R_SS]);
++
++ /* Special segments. */
++ nvmm_set_segment(&state->segs[NVMM_X64_SEG_GDT], &env->gdt);
++ nvmm_set_segment(&state->segs[NVMM_X64_SEG_LDT], &env->ldt);
++ nvmm_set_segment(&state->segs[NVMM_X64_SEG_TR], &env->tr);
++ nvmm_set_segment(&state->segs[NVMM_X64_SEG_IDT], &env->idt);
++
++ /* Control registers. */
++ state->crs[NVMM_X64_CR_CR0] = env->cr[0];
++ state->crs[NVMM_X64_CR_CR2] = env->cr[2];
++ state->crs[NVMM_X64_CR_CR3] = env->cr[3];
++ state->crs[NVMM_X64_CR_CR4] = env->cr[4];
++ state->crs[NVMM_X64_CR_CR8] = qcpu->tpr;
++ state->crs[NVMM_X64_CR_XCR0] = env->xcr0;
++
++ /* Debug registers. */
++ state->drs[NVMM_X64_DR_DR0] = env->dr[0];
++ state->drs[NVMM_X64_DR_DR1] = env->dr[1];
++ state->drs[NVMM_X64_DR_DR2] = env->dr[2];
++ state->drs[NVMM_X64_DR_DR3] = env->dr[3];
++ state->drs[NVMM_X64_DR_DR6] = env->dr[6];
++ state->drs[NVMM_X64_DR_DR7] = env->dr[7];
++
++ /* FPU. */
++ state->fpu.fx_cw = env->fpuc;
++ state->fpu.fx_sw = (env->fpus & ~0x3800) | ((env->fpstt & 0x7) << 11);
++ state->fpu.fx_tw = 0;
++ for (i = 0; i < 8; i++) {
++ state->fpu.fx_tw |= (!env->fptags[i]) << i;
++ }
++ state->fpu.fx_opcode = env->fpop;
++ state->fpu.fx_ip.fa_64 = env->fpip;
++ state->fpu.fx_dp.fa_64 = env->fpdp;
++ state->fpu.fx_mxcsr = env->mxcsr;
++ state->fpu.fx_mxcsr_mask = 0x0000FFFF;
++ assert(sizeof(state->fpu.fx_87_ac) == sizeof(env->fpregs));
++ memcpy(state->fpu.fx_87_ac, env->fpregs, sizeof(env->fpregs));
++ for (i = 0; i < CPU_NB_REGS; i++) {
++ memcpy(&state->fpu.fx_xmm[i].xmm_bytes[0],
++ &env->xmm_regs[i].ZMM_Q(0), 8);
++ memcpy(&state->fpu.fx_xmm[i].xmm_bytes[8],
++ &env->xmm_regs[i].ZMM_Q(1), 8);
++ }
++
++ /* MSRs. */
++ state->msrs[NVMM_X64_MSR_EFER] = env->efer;
++ state->msrs[NVMM_X64_MSR_STAR] = env->star;
++#ifdef TARGET_X86_64
++ state->msrs[NVMM_X64_MSR_LSTAR] = env->lstar;
++ state->msrs[NVMM_X64_MSR_CSTAR] = env->cstar;
++ state->msrs[NVMM_X64_MSR_SFMASK] = env->fmask;
++ state->msrs[NVMM_X64_MSR_KERNELGSBASE] = env->kernelgsbase;
++#endif
++ state->msrs[NVMM_X64_MSR_SYSENTER_CS] = env->sysenter_cs;
++ state->msrs[NVMM_X64_MSR_SYSENTER_ESP] = env->sysenter_esp;
++ state->msrs[NVMM_X64_MSR_SYSENTER_EIP] = env->sysenter_eip;
++ state->msrs[NVMM_X64_MSR_PAT] = env->pat;
++ state->msrs[NVMM_X64_MSR_TSC] = env->tsc;
++
++ bitmap =
++ NVMM_X64_STATE_SEGS |
++ NVMM_X64_STATE_GPRS |
++ NVMM_X64_STATE_CRS |
++ NVMM_X64_STATE_DRS |
++ NVMM_X64_STATE_MSRS |
++ NVMM_X64_STATE_FPU;
++
++ ret = nvmm_vcpu_setstate(mach, vcpu, bitmap);
++ if (ret == -1) {
++ error_report("NVMM: Failed to set virtual processor context,"
++ " error=%d", errno);
++ }
++}
++
++static void
++nvmm_get_segment(SegmentCache *qseg, const struct nvmm_x64_state_seg *nseg)
++{
++ qseg->selector = nseg->selector;
++ qseg->limit = nseg->limit;
++ qseg->base = nseg->base;
++
++ qseg->flags =
++ __SHIFTIN((uint32_t)nseg->attrib.type, DESC_TYPE_MASK) |
++ __SHIFTIN((uint32_t)nseg->attrib.s, DESC_S_MASK) |
++ __SHIFTIN((uint32_t)nseg->attrib.dpl, DESC_DPL_MASK) |
++ __SHIFTIN((uint32_t)nseg->attrib.p, DESC_P_MASK) |
++ __SHIFTIN((uint32_t)nseg->attrib.avl, DESC_AVL_MASK) |
++ __SHIFTIN((uint32_t)nseg->attrib.l, DESC_L_MASK) |
++ __SHIFTIN((uint32_t)nseg->attrib.def, DESC_B_MASK) |
++ __SHIFTIN((uint32_t)nseg->attrib.g, DESC_G_MASK);
++}
++
++static void
++nvmm_get_registers(CPUState *cpu)
++{
++ struct CPUX86State *env = (CPUArchState *)cpu->env_ptr;
++ struct nvmm_machine *mach = get_nvmm_mach();
++ struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu);
++ struct nvmm_vcpu *vcpu = &qcpu->vcpu;
++ X86CPU *x86_cpu = X86_CPU(cpu);
++ struct nvmm_x64_state *state = vcpu->state;
++ uint64_t bitmap, tpr;
++ size_t i;
++ int ret;
++
++ assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
++
++ bitmap =
++ NVMM_X64_STATE_SEGS |
++ NVMM_X64_STATE_GPRS |
++ NVMM_X64_STATE_CRS |
++ NVMM_X64_STATE_DRS |
++ NVMM_X64_STATE_MSRS |
++ NVMM_X64_STATE_FPU;
++
++ ret = nvmm_vcpu_getstate(mach, vcpu, bitmap);
++ if (ret == -1) {
++ error_report("NVMM: Failed to get virtual processor context,"
++ " error=%d", errno);
++ }
++
++ /* GPRs. */
++ env->regs[R_EAX] = state->gprs[NVMM_X64_GPR_RAX];
++ env->regs[R_ECX] = state->gprs[NVMM_X64_GPR_RCX];
++ env->regs[R_EDX] = state->gprs[NVMM_X64_GPR_RDX];
++ env->regs[R_EBX] = state->gprs[NVMM_X64_GPR_RBX];
++ env->regs[R_ESP] = state->gprs[NVMM_X64_GPR_RSP];
++ env->regs[R_EBP] = state->gprs[NVMM_X64_GPR_RBP];
++ env->regs[R_ESI] = state->gprs[NVMM_X64_GPR_RSI];
++ env->regs[R_EDI] = state->gprs[NVMM_X64_GPR_RDI];
++#ifdef TARGET_X86_64
++ env->regs[R_R8] = state->gprs[NVMM_X64_GPR_R8];
++ env->regs[R_R9] = state->gprs[NVMM_X64_GPR_R9];
++ env->regs[R_R10] = state->gprs[NVMM_X64_GPR_R10];
++ env->regs[R_R11] = state->gprs[NVMM_X64_GPR_R11];
++ env->regs[R_R12] = state->gprs[NVMM_X64_GPR_R12];
++ env->regs[R_R13] = state->gprs[NVMM_X64_GPR_R13];
++ env->regs[R_R14] = state->gprs[NVMM_X64_GPR_R14];
++ env->regs[R_R15] = state->gprs[NVMM_X64_GPR_R15];
++#endif
++
++ /* RIP and RFLAGS. */
++ env->eip = state->gprs[NVMM_X64_GPR_RIP];
++ env->eflags = state->gprs[NVMM_X64_GPR_RFLAGS];
++
++ /* Segments. */
++ nvmm_get_segment(&env->segs[R_ES], &state->segs[NVMM_X64_SEG_ES]);
++ nvmm_get_segment(&env->segs[R_CS], &state->segs[NVMM_X64_SEG_CS]);
++ nvmm_get_segment(&env->segs[R_SS], &state->segs[NVMM_X64_SEG_SS]);
++ nvmm_get_segment(&env->segs[R_DS], &state->segs[NVMM_X64_SEG_DS]);
++ nvmm_get_segment(&env->segs[R_FS], &state->segs[NVMM_X64_SEG_FS]);
++ nvmm_get_segment(&env->segs[R_GS], &state->segs[NVMM_X64_SEG_GS]);
++
++ /* Special segments. */
++ nvmm_get_segment(&env->gdt, &state->segs[NVMM_X64_SEG_GDT]);
++ nvmm_get_segment(&env->ldt, &state->segs[NVMM_X64_SEG_LDT]);
++ nvmm_get_segment(&env->tr, &state->segs[NVMM_X64_SEG_TR]);
++ nvmm_get_segment(&env->idt, &state->segs[NVMM_X64_SEG_IDT]);
++
++ /* Control registers. */
++ env->cr[0] = state->crs[NVMM_X64_CR_CR0];
++ env->cr[2] = state->crs[NVMM_X64_CR_CR2];
++ env->cr[3] = state->crs[NVMM_X64_CR_CR3];
++ env->cr[4] = state->crs[NVMM_X64_CR_CR4];
++ tpr = state->crs[NVMM_X64_CR_CR8];
++ if (tpr != qcpu->tpr) {
++ qcpu->tpr = tpr;
++ cpu_set_apic_tpr(x86_cpu->apic_state, tpr);
++ }
++ env->xcr0 = state->crs[NVMM_X64_CR_XCR0];
++
++ /* Debug registers. */
++ env->dr[0] = state->drs[NVMM_X64_DR_DR0];
++ env->dr[1] = state->drs[NVMM_X64_DR_DR1];
++ env->dr[2] = state->drs[NVMM_X64_DR_DR2];
++ env->dr[3] = state->drs[NVMM_X64_DR_DR3];
++ env->dr[6] = state->drs[NVMM_X64_DR_DR6];
++ env->dr[7] = state->drs[NVMM_X64_DR_DR7];
++
++ /* FPU. */
++ env->fpuc = state->fpu.fx_cw;
++ env->fpstt = (state->fpu.fx_sw >> 11) & 0x7;
++ env->fpus = state->fpu.fx_sw & ~0x3800;
++ for (i = 0; i < 8; i++) {
++ env->fptags[i] = !((state->fpu.fx_tw >> i) & 1);
++ }
++ env->fpop = state->fpu.fx_opcode;
++ env->fpip = state->fpu.fx_ip.fa_64;
++ env->fpdp = state->fpu.fx_dp.fa_64;
++ env->mxcsr = state->fpu.fx_mxcsr;
++ assert(sizeof(state->fpu.fx_87_ac) == sizeof(env->fpregs));
++ memcpy(env->fpregs, state->fpu.fx_87_ac, sizeof(env->fpregs));
++ for (i = 0; i < CPU_NB_REGS; i++) {
++ memcpy(&env->xmm_regs[i].ZMM_Q(0),
++ &state->fpu.fx_xmm[i].xmm_bytes[0], 8);
++ memcpy(&env->xmm_regs[i].ZMM_Q(1),
++ &state->fpu.fx_xmm[i].xmm_bytes[8], 8);
++ }
++
++ /* MSRs. */
++ env->efer = state->msrs[NVMM_X64_MSR_EFER];
++ env->star = state->msrs[NVMM_X64_MSR_STAR];
++#ifdef TARGET_X86_64
++ env->lstar = state->msrs[NVMM_X64_MSR_LSTAR];
++ env->cstar = state->msrs[NVMM_X64_MSR_CSTAR];
++ env->fmask = state->msrs[NVMM_X64_MSR_SFMASK];
++ env->kernelgsbase = state->msrs[NVMM_X64_MSR_KERNELGSBASE];
++#endif
++ env->sysenter_cs = state->msrs[NVMM_X64_MSR_SYSENTER_CS];
++ env->sysenter_esp = state->msrs[NVMM_X64_MSR_SYSENTER_ESP];
++ env->sysenter_eip = state->msrs[NVMM_X64_MSR_SYSENTER_EIP];
++ env->pat = state->msrs[NVMM_X64_MSR_PAT];
++ env->tsc = state->msrs[NVMM_X64_MSR_TSC];
++
++ x86_update_hflags(env);
++}
++
++static bool
++nvmm_can_take_int(CPUState *cpu)
++{
++ struct CPUX86State *env = (CPUArchState *)cpu->env_ptr;
++ struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu);
++ struct nvmm_vcpu *vcpu = &qcpu->vcpu;
++ struct nvmm_machine *mach = get_nvmm_mach();
++
++ if (qcpu->int_window_exit) {
++ return false;
++ }
++
++ if (qcpu->int_shadow || !(env->eflags & IF_MASK)) {
++ struct nvmm_x64_state *state = vcpu->state;
++
++ /* Exit on interrupt window. */
++ nvmm_vcpu_getstate(mach, vcpu, NVMM_X64_STATE_INTR);
++ state->intr.int_window_exiting = 1;
++ nvmm_vcpu_setstate(mach, vcpu, NVMM_X64_STATE_INTR);
++
++ return false;
++ }
++
++ return true;
++}
++
++static bool
++nvmm_can_take_nmi(CPUState *cpu)
++{
++ struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu);
++
++ /*
++ * Contrary to INTs, NMIs always schedule an exit when they are
++ * completed. Therefore, if window-exiting is enabled, it means
++ * NMIs are blocked.
++ */
++ if (qcpu->nmi_window_exit) {
++ return false;
++ }
++
++ return true;
++}
++
++/*
++ * Called before the VCPU is run. We inject events generated by the I/O
++ * thread, and synchronize the guest TPR.
++ */
++static void
++nvmm_vcpu_pre_run(CPUState *cpu)
++{
++ struct CPUX86State *env = (CPUArchState *)cpu->env_ptr;
++ struct nvmm_machine *mach = get_nvmm_mach();
++ struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu);
++ struct nvmm_vcpu *vcpu = &qcpu->vcpu;
++ X86CPU *x86_cpu = X86_CPU(cpu);
++ struct nvmm_x64_state *state = vcpu->state;
++ struct nvmm_vcpu_event *event = vcpu->event;
++ bool has_event = false;
++ bool sync_tpr = false;
++ uint8_t tpr;
++ int ret;
++
++ qemu_mutex_lock_iothread();
++
++ tpr = cpu_get_apic_tpr(x86_cpu->apic_state);
++ if (tpr != qcpu->tpr) {
++ qcpu->tpr = tpr;
++ sync_tpr = true;
++ }
++
++ /*
++ * Force the VCPU out of its inner loop to process any INIT requests
++ * or commit pending TPR access.
++ */
++ if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
++ cpu->exit_request = 1;
++ }
++
++ if (!has_event && (cpu->interrupt_request & CPU_INTERRUPT_NMI)) {
++ if (nvmm_can_take_nmi(cpu)) {
++ cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
++ event->type = NVMM_VCPU_EVENT_INTR;
++ event->vector = 2;
++ has_event = true;
++ }
++ }
++
++ if (!has_event && (cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
++ if (nvmm_can_take_int(cpu)) {
++ cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
++ event->type = NVMM_VCPU_EVENT_INTR;
++ event->vector = cpu_get_pic_interrupt(env);
++ has_event = true;
++ }
++ }
++
++ /* Don't want SMIs. */
++ if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
++ cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
++ }
++
++ if (sync_tpr) {
++ ret = nvmm_vcpu_getstate(mach, vcpu, NVMM_X64_STATE_CRS);
++ if (ret == -1) {
++ error_report("NVMM: Failed to get CPU state,"
++ " error=%d", errno);
++ }
++
++ state->crs[NVMM_X64_CR_CR8] = qcpu->tpr;
++
++ ret = nvmm_vcpu_setstate(mach, vcpu, NVMM_X64_STATE_CRS);
++ if (ret == -1) {
++ error_report("NVMM: Failed to set CPU state,"
++ " error=%d", errno);
++ }
++ }
++
++ if (has_event) {
++ ret = nvmm_vcpu_inject(mach, vcpu);
++ if (ret == -1) {
++ error_report("NVMM: Failed to inject event,"
++ " error=%d", errno);
++ }
++ }
++
++ qemu_mutex_unlock_iothread();
++}
++
++/*
++ * Called after the VCPU ran. We synchronize the host view of the TPR and
++ * RFLAGS.
++ */
++static void
++nvmm_vcpu_post_run(CPUState *cpu, struct nvmm_vcpu_exit *exit)
++{
++ struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu);
++ struct CPUX86State *env = (CPUArchState *)cpu->env_ptr;
++ X86CPU *x86_cpu = X86_CPU(cpu);
++ uint64_t tpr;
++
++ env->eflags = exit->exitstate.rflags;
++ qcpu->int_shadow = exit->exitstate.int_shadow;
++ qcpu->int_window_exit = exit->exitstate.int_window_exiting;
++ qcpu->nmi_window_exit = exit->exitstate.nmi_window_exiting;
++
++ tpr = exit->exitstate.cr8;
++ if (qcpu->tpr != tpr) {
++ qcpu->tpr = tpr;
++ qemu_mutex_lock_iothread();
++ cpu_set_apic_tpr(x86_cpu->apic_state, qcpu->tpr);
++ qemu_mutex_unlock_iothread();
++ }
++}
++
++/* -------------------------------------------------------------------------- */
++
++static void
++nvmm_io_callback(struct nvmm_io *io)
++{
++ MemTxAttrs attrs = { 0 };
++ int ret;
++
++ ret = address_space_rw(&address_space_io, io->port, attrs, io->data,
++ io->size, !io->in);
++ if (ret != MEMTX_OK) {
++ error_report("NVMM: I/O Transaction Failed "
++ "[%s, port=%u, size=%zu]", (io->in ? "in" : "out"),
++ io->port, io->size);
++ }
++
++ /* Needed, otherwise infinite loop. */
++ current_cpu->vcpu_dirty = false;
++}
++
++static void
++nvmm_mem_callback(struct nvmm_mem *mem)
++{
++ cpu_physical_memory_rw(mem->gpa, mem->data, mem->size, mem->write);
++
++ /* XXX Needed, otherwise infinite loop. */
++ current_cpu->vcpu_dirty = false;
++}
++
++static struct nvmm_assist_callbacks nvmm_callbacks = {
++ .io = nvmm_io_callback,
++ .mem = nvmm_mem_callback
++};
++
++/* -------------------------------------------------------------------------- */
++
++static int
++nvmm_handle_mem(struct nvmm_machine *mach, struct nvmm_vcpu *vcpu)
++{
++ int ret;
++
++ ret = nvmm_assist_mem(mach, vcpu);
++ if (ret == -1) {
++ error_report("NVMM: Mem Assist Failed [gpa=%p]",
++ (void *)vcpu->exit->u.mem.gpa);
++ }
++
++ return ret;
++}
++
++static int
++nvmm_handle_io(struct nvmm_machine *mach, struct nvmm_vcpu *vcpu)
++{
++ int ret;
++
++ ret = nvmm_assist_io(mach, vcpu);
++ if (ret == -1) {
++ error_report("NVMM: I/O Assist Failed [port=%d]",
++ (int)vcpu->exit->u.io.port);
++ }
++
++ return ret;
++}
++
++static int
++nvmm_handle_rdmsr(struct nvmm_machine *mach, CPUState *cpu,
++ struct nvmm_vcpu_exit *exit)
++{
++ struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu);
++ struct nvmm_vcpu *vcpu = &qcpu->vcpu;
++ X86CPU *x86_cpu = X86_CPU(cpu);
++ struct nvmm_x64_state *state = vcpu->state;
++ uint64_t val;
++ int ret;
++
++ switch (exit->u.rdmsr.msr) {
++ case MSR_IA32_APICBASE:
++ val = cpu_get_apic_base(x86_cpu->apic_state);
++ break;
++ case MSR_MTRRcap:
++ case MSR_MTRRdefType:
++ case MSR_MCG_CAP:
++ case MSR_MCG_STATUS:
++ val = 0;
++ break;
++ default: /* More MSRs to add? */
++ val = 0;
++ error_report("NVMM: Unexpected RDMSR 0x%x, ignored",
++ exit->u.rdmsr.msr);
++ break;
++ }
++
++ ret = nvmm_vcpu_getstate(mach, vcpu, NVMM_X64_STATE_GPRS);
++ if (ret == -1) {
++ return -1;
++ }
++
++ state->gprs[NVMM_X64_GPR_RAX] = (val & 0xFFFFFFFF);
++ state->gprs[NVMM_X64_GPR_RDX] = (val >> 32);
++ state->gprs[NVMM_X64_GPR_RIP] = exit->u.rdmsr.npc;
++
++ ret = nvmm_vcpu_setstate(mach, vcpu, NVMM_X64_STATE_GPRS);
++ if (ret == -1) {
++ return -1;
++ }
++
++ return 0;
++}
++
++static int
++nvmm_handle_wrmsr(struct nvmm_machine *mach, CPUState *cpu,
++ struct nvmm_vcpu_exit *exit)
++{
++ struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu);
++ struct nvmm_vcpu *vcpu = &qcpu->vcpu;
++ X86CPU *x86_cpu = X86_CPU(cpu);
++ struct nvmm_x64_state *state = vcpu->state;
++ uint64_t val;
++ int ret;
++
++ val = exit->u.wrmsr.val;
++
++ switch (exit->u.wrmsr.msr) {
++ case MSR_IA32_APICBASE:
++ cpu_set_apic_base(x86_cpu->apic_state, val);
++ break;
++ case MSR_MTRRdefType:
++ case MSR_MCG_STATUS:
++ break;
++ default: /* More MSRs to add? */
++ error_report("NVMM: Unexpected WRMSR 0x%x [val=0x%lx], ignored",
++ exit->u.wrmsr.msr, val);
++ break;
++ }
++
++ ret = nvmm_vcpu_getstate(mach, vcpu, NVMM_X64_STATE_GPRS);
++ if (ret == -1) {
++ return -1;
++ }
++
++ state->gprs[NVMM_X64_GPR_RIP] = exit->u.wrmsr.npc;
++
++ ret = nvmm_vcpu_setstate(mach, vcpu, NVMM_X64_STATE_GPRS);
++ if (ret == -1) {
++ return -1;
++ }
++
++ return 0;
++}
++
++static int
++nvmm_handle_halted(struct nvmm_machine *mach, CPUState *cpu,
++ struct nvmm_vcpu_exit *exit)
++{
++ struct CPUX86State *env = (CPUArchState *)cpu->env_ptr;
++ int ret = 0;
++
++ qemu_mutex_lock_iothread();
++
++ if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
++ (env->eflags & IF_MASK)) &&
++ !(cpu->interrupt_request & CPU_INTERRUPT_NMI)) {
++ cpu->exception_index = EXCP_HLT;
++ cpu->halted = true;
++ ret = 1;
++ }
++
++ qemu_mutex_unlock_iothread();
++
++ return ret;
++}
++
++static int
++nvmm_inject_ud(struct nvmm_machine *mach, struct nvmm_vcpu *vcpu)
++{
++ struct nvmm_vcpu_event *event = vcpu->event;
++
++ event->type = NVMM_VCPU_EVENT_EXCP;
++ event->vector = 6;
++ event->u.excp.error = 0;
++
++ return nvmm_vcpu_inject(mach, vcpu);
++}
++
++static int
++nvmm_vcpu_loop(CPUState *cpu)
++{
++ struct CPUX86State *env = (CPUArchState *)cpu->env_ptr;
++ struct nvmm_machine *mach = get_nvmm_mach();
++ struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu);
++ struct nvmm_vcpu *vcpu = &qcpu->vcpu;
++ X86CPU *x86_cpu = X86_CPU(cpu);
++ struct nvmm_vcpu_exit *exit = vcpu->exit;
++ int ret;
++
++ /*
++ * Some asynchronous events must be handled outside of the inner
++ * VCPU loop. They are handled here.
++ */
++ if (cpu->interrupt_request & CPU_INTERRUPT_INIT) {
++ nvmm_cpu_synchronize_state(cpu);
++ do_cpu_init(x86_cpu);
++ /* set int/nmi windows back to the reset state */
++ }
++ if (cpu->interrupt_request & CPU_INTERRUPT_POLL) {
++ cpu->interrupt_request &= ~CPU_INTERRUPT_POLL;
++ apic_poll_irq(x86_cpu->apic_state);
++ }
++ if (((cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
++ (env->eflags & IF_MASK)) ||
++ (cpu->interrupt_request & CPU_INTERRUPT_NMI)) {
++ cpu->halted = false;
++ }
++ if (cpu->interrupt_request & CPU_INTERRUPT_SIPI) {
++ nvmm_cpu_synchronize_state(cpu);
++ do_cpu_sipi(x86_cpu);
++ }
++ if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
++ cpu->interrupt_request &= ~CPU_INTERRUPT_TPR;
++ nvmm_cpu_synchronize_state(cpu);
++ apic_handle_tpr_access_report(x86_cpu->apic_state, env->eip,
++ env->tpr_access_type);
++ }
++
++ if (cpu->halted) {
++ cpu->exception_index = EXCP_HLT;
++ atomic_set(&cpu->exit_request, false);
++ return 0;
++ }
++
++ qemu_mutex_unlock_iothread();
++ cpu_exec_start(cpu);
++
++ /*
++ * Inner VCPU loop.
++ */
++ do {
++ if (cpu->vcpu_dirty) {
++ nvmm_set_registers(cpu);
++ cpu->vcpu_dirty = false;
++ }
++
++ if (qcpu->stop) {
++ cpu->exception_index = EXCP_INTERRUPT;
++ qcpu->stop = false;
++ ret = 1;
++ break;
++ }
++
++ nvmm_vcpu_pre_run(cpu);
++
++ if (atomic_read(&cpu->exit_request)) {
++ qemu_cpu_kick_self();
++ }
++
++ ret = nvmm_vcpu_run(mach, vcpu);
++ if (ret == -1) {
++ error_report("NVMM: Failed to exec a virtual processor,"
++ " error=%d", errno);
++ break;
++ }
++
++ nvmm_vcpu_post_run(cpu, exit);
++
++ switch (exit->reason) {
++ case NVMM_VCPU_EXIT_NONE:
++ break;
++ case NVMM_VCPU_EXIT_MEMORY:
++ ret = nvmm_handle_mem(mach, vcpu);
++ break;
++ case NVMM_VCPU_EXIT_IO:
++ ret = nvmm_handle_io(mach, vcpu);
++ break;
++ case NVMM_VCPU_EXIT_INT_READY:
++ case NVMM_VCPU_EXIT_NMI_READY:
++ case NVMM_VCPU_EXIT_TPR_CHANGED:
++ break;
++ case NVMM_VCPU_EXIT_HALTED:
++ ret = nvmm_handle_halted(mach, cpu, exit);
++ break;
++ case NVMM_VCPU_EXIT_SHUTDOWN:
++ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
++ cpu->exception_index = EXCP_INTERRUPT;
++ ret = 1;
++ break;
++ case NVMM_VCPU_EXIT_RDMSR:
++ ret = nvmm_handle_rdmsr(mach, cpu, exit);
++ break;
++ case NVMM_VCPU_EXIT_WRMSR:
++ ret = nvmm_handle_wrmsr(mach, cpu, exit);
++ break;
++ case NVMM_VCPU_EXIT_MONITOR:
++ case NVMM_VCPU_EXIT_MWAIT:
++ ret = nvmm_inject_ud(mach, vcpu);
++ break;
++ default:
++ error_report("NVMM: Unexpected VM exit code 0x%lx [hw=0x%lx]",
++ exit->reason, exit->u.inv.hwcode);
++ nvmm_get_registers(cpu);
++ qemu_mutex_lock_iothread();
++ qemu_system_guest_panicked(cpu_get_crash_info(cpu));
++ qemu_mutex_unlock_iothread();
++ ret = -1;
++ break;
++ }
++ } while (ret == 0);
++
++ cpu_exec_end(cpu);
++ qemu_mutex_lock_iothread();
++ current_cpu = cpu;
++
++ atomic_set(&cpu->exit_request, false);
++
++ return ret < 0;
++}
++
++/* -------------------------------------------------------------------------- */
++
++static void
++do_nvmm_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data arg)
++{
++ nvmm_get_registers(cpu);
++ cpu->vcpu_dirty = true;
++}
++
++static void
++do_nvmm_cpu_synchronize_post_reset(CPUState *cpu, run_on_cpu_data arg)
++{
++ nvmm_set_registers(cpu);
++ cpu->vcpu_dirty = false;
++}
++
++static void
++do_nvmm_cpu_synchronize_post_init(CPUState *cpu, run_on_cpu_data arg)
++{
++ nvmm_set_registers(cpu);
++ cpu->vcpu_dirty = false;
++}
++
++static void
++do_nvmm_cpu_synchronize_pre_loadvm(CPUState *cpu, run_on_cpu_data arg)
++{
++ cpu->vcpu_dirty = true;
++}
++
++void nvmm_cpu_synchronize_state(CPUState *cpu)
++{
++ if (!cpu->vcpu_dirty) {
++ run_on_cpu(cpu, do_nvmm_cpu_synchronize_state, RUN_ON_CPU_NULL);
++ }
++}
++
++void nvmm_cpu_synchronize_post_reset(CPUState *cpu)
++{
++ run_on_cpu(cpu, do_nvmm_cpu_synchronize_post_reset, RUN_ON_CPU_NULL);
++}
++
++void nvmm_cpu_synchronize_post_init(CPUState *cpu)
++{
++ run_on_cpu(cpu, do_nvmm_cpu_synchronize_post_init, RUN_ON_CPU_NULL);
++}
++
++void nvmm_cpu_synchronize_pre_loadvm(CPUState *cpu)
++{
++ run_on_cpu(cpu, do_nvmm_cpu_synchronize_pre_loadvm, RUN_ON_CPU_NULL);
++}
++
++/* -------------------------------------------------------------------------- */
++
++static Error *nvmm_migration_blocker;
++
++static void
++nvmm_ipi_signal(int sigcpu)
++{
++ struct qemu_vcpu *qcpu;
++
++ if (current_cpu) {
++ qcpu = get_qemu_vcpu(current_cpu);
++ qcpu->stop = true;
++ }
++}
++
++static void
++nvmm_init_cpu_signals(void)
++{
++ struct sigaction sigact;
++ sigset_t set;
++
++ /* Install the IPI handler. */
++ memset(&sigact, 0, sizeof(sigact));
++ sigact.sa_handler = nvmm_ipi_signal;
++ sigaction(SIG_IPI, &sigact, NULL);
++
++ /* Allow IPIs on the current thread. */
++ sigprocmask(SIG_BLOCK, NULL, &set);
++ sigdelset(&set, SIG_IPI);
++ pthread_sigmask(SIG_SETMASK, &set, NULL);
++}
++
++int
++nvmm_init_vcpu(CPUState *cpu)
++{
++ struct nvmm_machine *mach = get_nvmm_mach();
++ struct nvmm_vcpu_conf_cpuid cpuid;
++ struct nvmm_vcpu_conf_tpr tpr;
++ Error *local_error = NULL;
++ struct qemu_vcpu *qcpu;
++ int ret, err;
++
++ nvmm_init_cpu_signals();
++
++ if (nvmm_migration_blocker == NULL) {
++ error_setg(&nvmm_migration_blocker,
++ "NVMM: Migration not supported");
++
++ (void)migrate_add_blocker(nvmm_migration_blocker, &local_error);
++ if (local_error) {
++ error_report_err(local_error);
++ migrate_del_blocker(nvmm_migration_blocker);
++ error_free(nvmm_migration_blocker);
++ return -EINVAL;
++ }
++ }
++
++ qcpu = g_malloc0(sizeof(*qcpu));
++ if (qcpu == NULL) {
++ error_report("NVMM: Failed to allocate VCPU context.");
++ return -ENOMEM;
++ }
++
++ ret = nvmm_vcpu_create(mach, cpu->cpu_index, &qcpu->vcpu);
++ if (ret == -1) {
++ err = errno;
++ error_report("NVMM: Failed to create a virtual processor,"
++ " error=%d", err);
++ g_free(qcpu);
++ return -err;
++ }
++
++ memset(&cpuid, 0, sizeof(cpuid));
++ cpuid.mask = 1;
++ cpuid.leaf = 0x00000001;
++ cpuid.u.mask.set.edx = CPUID_MCE | CPUID_MCA | CPUID_MTRR;
++ ret = nvmm_vcpu_configure(mach, &qcpu->vcpu, NVMM_VCPU_CONF_CPUID,
++ &cpuid);
++ if (ret == -1) {
++ err = errno;
++ error_report("NVMM: Failed to configure a virtual processor,"
++ " error=%d", err);
++ g_free(qcpu);
++ return -err;
++ }
++
++ ret = nvmm_vcpu_configure(mach, &qcpu->vcpu, NVMM_VCPU_CONF_CALLBACKS,
++ &nvmm_callbacks);
++ if (ret == -1) {
++ err = errno;
++ error_report("NVMM: Failed to configure a virtual processor,"
++ " error=%d", err);
++ g_free(qcpu);
++ return -err;
++ }
++
++ if (qemu_mach.cap.arch.vcpu_conf_support & NVMM_CAP_ARCH_VCPU_CONF_TPR) {
++ memset(&tpr, 0, sizeof(tpr));
++ tpr.exit_changed = 1;
++ ret = nvmm_vcpu_configure(mach, &qcpu->vcpu, NVMM_VCPU_CONF_TPR, &tpr);
++ if (ret == -1) {
++ err = errno;
++ error_report("NVMM: Failed to configure a virtual processor,"
++ " error=%d", err);
++ g_free(qcpu);
++ return -err;
++ }
++ }
++
++ cpu->vcpu_dirty = true;
++ cpu->hax_vcpu = (struct hax_vcpu_state *)qcpu;
++
++ return 0;
++}
++
++int
++nvmm_vcpu_exec(CPUState *cpu)
++{
++ int ret, fatal;
++
++ while (1) {
++ if (cpu->exception_index >= EXCP_INTERRUPT) {
++ ret = cpu->exception_index;
++ cpu->exception_index = -1;
++ break;
++ }
++
++ fatal = nvmm_vcpu_loop(cpu);
++
++ if (fatal) {
++ error_report("NVMM: Failed to execute a VCPU.");
++ abort();
++ }
++ }
++
++ return ret;
++}
++
++void
++nvmm_destroy_vcpu(CPUState *cpu)
++{
++ struct nvmm_machine *mach = get_nvmm_mach();
++ struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu);
++
++ nvmm_vcpu_destroy(mach, &qcpu->vcpu);
++ g_free(cpu->hax_vcpu);
++}
++
++/* -------------------------------------------------------------------------- */
++
++static void
++nvmm_update_mapping(hwaddr start_pa, ram_addr_t size, uintptr_t hva,
++ bool add, bool rom, const char *name)
++{
++ struct nvmm_machine *mach = get_nvmm_mach();
++ int ret, prot;
++
++ if (add) {
++ prot = PROT_READ | PROT_EXEC;
++ if (!rom) {
++ prot |= PROT_WRITE;
++ }
++ ret = nvmm_gpa_map(mach, hva, start_pa, size, prot);
++ } else {
++ ret = nvmm_gpa_unmap(mach, hva, start_pa, size);
++ }
++
++ if (ret == -1) {
++ error_report("NVMM: Failed to %s GPA range '%s' PA:%p, "
++ "Size:%p bytes, HostVA:%p, error=%d",
++ (add ? "map" : "unmap"), name, (void *)(uintptr_t)start_pa,
++ (void *)size, (void *)hva, errno);
++ }
++}
++
++static void
++nvmm_process_section(MemoryRegionSection *section, int add)
++{
++ MemoryRegion *mr = section->mr;
++ hwaddr start_pa = section->offset_within_address_space;
++ ram_addr_t size = int128_get64(section->size);
++ unsigned int delta;
++ uintptr_t hva;
++
++ if (!memory_region_is_ram(mr)) {
++ return;
++ }
++
++ /* Adjust start_pa and size so that they are page-aligned. */
++ delta = qemu_real_host_page_size - (start_pa & ~qemu_real_host_page_mask);
++ delta &= ~qemu_real_host_page_mask;
++ if (delta > size) {
++ return;
++ }
++ start_pa += delta;
++ size -= delta;
++ size &= qemu_real_host_page_mask;
++ if (!size || (start_pa & ~qemu_real_host_page_mask)) {
++ return;
++ }
++
++ hva = (uintptr_t)memory_region_get_ram_ptr(mr) +
++ section->offset_within_region + delta;
++
++ nvmm_update_mapping(start_pa, size, hva, add,
++ memory_region_is_rom(mr), mr->name);
++}
++
++static void
++nvmm_region_add(MemoryListener *listener, MemoryRegionSection *section)
++{
++ memory_region_ref(section->mr);
++ nvmm_process_section(section, 1);
++}
++
++static void
++nvmm_region_del(MemoryListener *listener, MemoryRegionSection *section)
++{
++ nvmm_process_section(section, 0);
++ memory_region_unref(section->mr);
++}
++
++static void
++nvmm_transaction_begin(MemoryListener *listener)
++{
++ /* nothing */
++}
++
++static void
++nvmm_transaction_commit(MemoryListener *listener)
++{
++ /* nothing */
++}
++
++static void
++nvmm_log_sync(MemoryListener *listener, MemoryRegionSection *section)
++{
++ MemoryRegion *mr = section->mr;
++
++ if (!memory_region_is_ram(mr)) {
++ return;
++ }
++
++ memory_region_set_dirty(mr, 0, int128_get64(section->size));
++}
++
++static MemoryListener nvmm_memory_listener = {
++ .begin = nvmm_transaction_begin,
++ .commit = nvmm_transaction_commit,
++ .region_add = nvmm_region_add,
++ .region_del = nvmm_region_del,
++ .log_sync = nvmm_log_sync,
++ .priority = 10,
++};
++
++static void
++nvmm_ram_block_added(RAMBlockNotifier *n, void *host, size_t size)
++{
++ struct nvmm_machine *mach = get_nvmm_mach();
++ uintptr_t hva = (uintptr_t)host;
++ int ret;
++
++ ret = nvmm_hva_map(mach, hva, size);
++
++ if (ret == -1) {
++ error_report("NVMM: Failed to map HVA, HostVA:%p "
++ "Size:%p bytes, error=%d",
++ (void *)hva, (void *)size, errno);
++ }
++}
++
++static struct RAMBlockNotifier nvmm_ram_notifier = {
++ .ram_block_added = nvmm_ram_block_added
++};
++
++/* -------------------------------------------------------------------------- */
++
++static void
++nvmm_handle_interrupt(CPUState *cpu, int mask)
++{
++ cpu->interrupt_request |= mask;
++
++ if (!qemu_cpu_is_self(cpu)) {
++ qemu_cpu_kick(cpu);
++ }
++}
++
++/* -------------------------------------------------------------------------- */
++
++static int
++nvmm_accel_init(MachineState *ms)
++{
++ int ret, err;
++
++ ret = nvmm_init();
++ if (ret == -1) {
++ err = errno;
++ error_report("NVMM: Initialization failed, error=%d", errno);
++ return -err;
++ }
++
++ ret = nvmm_capability(&qemu_mach.cap);
++ if (ret == -1) {
++ err = errno;
++ error_report("NVMM: Unable to fetch capability, error=%d", errno);
++ return -err;
++ }
++ if (qemu_mach.cap.version != 1) {
++ error_report("NVMM: Unsupported version %u", qemu_mach.cap.version);
++ return -EPROGMISMATCH;
++ }
++ if (qemu_mach.cap.state_size != sizeof(struct nvmm_x64_state)) {
++ error_report("NVMM: Wrong state size %u", qemu_mach.cap.state_size);
++ return -EPROGMISMATCH;
++ }
++
++ ret = nvmm_machine_create(&qemu_mach.mach);
++ if (ret == -1) {
++ err = errno;
++ error_report("NVMM: Machine creation failed, error=%d", errno);
++ return -err;
++ }
++
++ memory_listener_register(&nvmm_memory_listener, &address_space_memory);
++ ram_block_notifier_add(&nvmm_ram_notifier);
++
++ cpu_interrupt_handler = nvmm_handle_interrupt;
++
++ printf("NetBSD Virtual Machine Monitor accelerator is operational\n");
++ return 0;
++}
++
++int
++nvmm_enabled(void)
++{
++ return nvmm_allowed;
++}
++
++static void
++nvmm_accel_class_init(ObjectClass *oc, void *data)
++{
++ AccelClass *ac = ACCEL_CLASS(oc);
++ ac->name = "NVMM";
++ ac->init_machine = nvmm_accel_init;
++ ac->allowed = &nvmm_allowed;
++}
++
++static const TypeInfo nvmm_accel_type = {
++ .name = ACCEL_CLASS_NAME("nvmm"),
++ .parent = TYPE_ACCEL,
++ .class_init = nvmm_accel_class_init,
++};
++
++static void
++nvmm_type_init(void)
++{
++ type_register_static(&nvmm_accel_type);
++}
++
++type_init(nvmm_type_init);
Index: pkgsrc/emulators/qemu51/patches/patch-target_sparc_translate.c
diff -u /dev/null pkgsrc/emulators/qemu51/patches/patch-target_sparc_translate.c:1.1
--- /dev/null Sat Feb 20 22:55:19 2021
+++ pkgsrc/emulators/qemu51/patches/patch-target_sparc_translate.c Sat Feb 20 22:55:19 2021
@@ -0,0 +1,24 @@
+$NetBSD: patch-target_sparc_translate.c,v 1.1 2021/02/20 22:55:19 ryoon Exp $
+
+Patch from upstream (not integrated there yet) to work around %pc/%npc
+being set to invalid values via ptrace, triggered by the NetBSD ptrace
+ATF tests. Real hardware seems to hardcode the lower bits to zero too.
+
+--- target/sparc/translate.c.orig 2020-08-11 21:17:15.000000000 +0200
++++ target/sparc/translate.c 2020-11-02 18:04:50.507211101 +0100
+@@ -4525,6 +4525,7 @@
+
+ r_tsptr = tcg_temp_new_ptr();
+ gen_load_trap_state_at_tl(r_tsptr, cpu_env);
++ tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, ~3);
+ tcg_gen_st_tl(cpu_tmp0, r_tsptr,
+ offsetof(trap_state, tpc));
+ tcg_temp_free_ptr(r_tsptr);
+@@ -4536,6 +4537,7 @@
+
+ r_tsptr = tcg_temp_new_ptr();
+ gen_load_trap_state_at_tl(r_tsptr, cpu_env);
++ tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, ~3);
+ tcg_gen_st_tl(cpu_tmp0, r_tsptr,
+ offsetof(trap_state, tnpc));
+ tcg_temp_free_ptr(r_tsptr);
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