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CVS commit: pkgsrc/cad
Module Name: pkgsrc
Committed By: ryoon
Date: Sun Dec 16 09:39:22 UTC 2018
Modified Files:
pkgsrc/cad: Makefile
Log Message:
Enable verilator
To generate a diff of this commit:
cvs rdiff -u -r1.96 -r1.97 pkgsrc/cad/Makefile
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: pkgsrc/cad/Makefile
diff -u pkgsrc/cad/Makefile:1.96 pkgsrc/cad/Makefile:1.97
--- pkgsrc/cad/Makefile:1.96 Sat Mar 17 22:20:13 2018
+++ pkgsrc/cad/Makefile Sun Dec 16 09:39:22 2018
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile,v 1.96 2018/03/17 22:20:13 mef Exp $
+# $NetBSD: Makefile,v 1.97 2018/12/16 09:39:22 ryoon Exp $
#
COMMENT= CAD tools
@@ -65,6 +65,7 @@ SUBDIR+= stdio-wcalc
SUBDIR+= tkgate
SUBDIR+= tnt-mmtl
SUBDIR+= transcalc
+SUBDIR+= verilator
SUBDIR+= verilog-mode
SUBDIR+= veriwell
SUBDIR+= wcalc
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