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CVS commit: pkgsrc/emulators/gxemul
Module Name: pkgsrc
Committed By: kamil
Date: Wed Mar 21 17:39:42 UTC 2018
Modified Files:
pkgsrc/emulators/gxemul: distinfo
pkgsrc/emulators/gxemul/patches: patch-ad patch-ag
patch-src_cpus_cpu_mips.cc patch-src_cpus_cpu_mips_instr.cc
patch-src_devices_dev__sh4.cc patch-src_machines_machine__pmax.cc
Added Files:
pkgsrc/emulators/gxemul/patches: patch-src_console_x11.cc
patch-src_cpus_cpu.cc patch-src_cpus_cpu__alpha.cc
patch-src_cpus_cpu__alpha__palcode.cc
patch-src_cpus_cpu__dyntrans.cc patch-src_cpus_cpu__m88k.cc
patch-src_cpus_cpu__m88k__instr.cc
patch-src_cpus_cpu__m88k__instr__loadstore.cc
patch-src_cpus_cpu__ppc.cc patch-src_cpus_cpu__ppc__instr.cc
patch-src_cpus_cpu__sh.cc patch-src_cpus_memory__alpha.cc
patch-src_cpus_memory__mips__v2p.cc patch-src_cpus_memory__ppc.cc
patch-src_cpus_memory__sh.cc patch-src_debugger_debugger.cc
patch-src_debugger_debugger__cmds.cc patch-src_devices_bus__pci.cc
patch-src_devices_dev__algor.cc
patch-src_devices_dev__dreamcast__gdrom.cc
patch-src_devices_dev__dreamcast__maple.cc
patch-src_devices_dev__lca.cc patch-src_devices_dev__pvr.cc
patch-src_devices_dev__sgi__mardigras.cc
patch-src_devices_dev__vga.cc patch-src_devices_dev__vr41xx.cc
patch-src_devices_dev__wdc.cc patch-src_disk_bootblock.cc
patch-src_disk_diskimage.cc patch-src_file_file__elf.cc
patch-src_file_file__raw.cc patch-src_machines_machine__landisk.cc
patch-src_machines_machine__test.cc patch-src_main_GXemul.cc
patch-src_old__main_emul.cc patch-src_old__main_main.cc
patch-src_old__main_memory.cc patch-src_old__main_settings.cc
patch-src_promemul_arcbios.cc patch-src_promemul_dec__prom.cc
patch-src_promemul_dreamcast.cc patch-src_promemul_ps2__bios.cc
patch-src_symbol_symbol.cc
Log Message:
gxemul: Fix build with clang 7svn
Fix C++11 literals, they are now fatal. Reverting to C++98 does not work
as it is, as this code uses C++11 extensions like 'PRIx32' macros.
Extend one int to long in order to handle all values in a switch() case.
No functional change intended.
To generate a diff of this commit:
cvs rdiff -u -r1.51 -r1.52 pkgsrc/emulators/gxemul/distinfo
cvs rdiff -u -r1.1 -r1.2 pkgsrc/emulators/gxemul/patches/patch-ad \
pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu_mips.cc \
pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu_mips_instr.cc \
pkgsrc/emulators/gxemul/patches/patch-src_machines_machine__pmax.cc
cvs rdiff -u -r1.4 -r1.5 pkgsrc/emulators/gxemul/patches/patch-ag
cvs rdiff -u -r0 -r1.1 \
pkgsrc/emulators/gxemul/patches/patch-src_console_x11.cc \
pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu.cc \
pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__alpha.cc \
pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__alpha__palcode.cc \
pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__dyntrans.cc \
pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__m88k.cc \
pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__m88k__instr.cc \
pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__m88k__instr__loadstore.cc \
pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__ppc.cc \
pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__ppc__instr.cc \
pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__sh.cc \
pkgsrc/emulators/gxemul/patches/patch-src_cpus_memory__alpha.cc \
pkgsrc/emulators/gxemul/patches/patch-src_cpus_memory__mips__v2p.cc \
pkgsrc/emulators/gxemul/patches/patch-src_cpus_memory__ppc.cc \
pkgsrc/emulators/gxemul/patches/patch-src_cpus_memory__sh.cc \
pkgsrc/emulators/gxemul/patches/patch-src_debugger_debugger.cc \
pkgsrc/emulators/gxemul/patches/patch-src_debugger_debugger__cmds.cc \
pkgsrc/emulators/gxemul/patches/patch-src_devices_bus__pci.cc \
pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__algor.cc \
pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__dreamcast__maple.cc \
pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__lca.cc \
pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__pvr.cc \
pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__sgi__mardigras.cc \
pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__vga.cc \
pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__vr41xx.cc \
pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__wdc.cc \
pkgsrc/emulators/gxemul/patches/patch-src_disk_bootblock.cc \
pkgsrc/emulators/gxemul/patches/patch-src_disk_diskimage.cc \
pkgsrc/emulators/gxemul/patches/patch-src_file_file__elf.cc \
pkgsrc/emulators/gxemul/patches/patch-src_file_file__raw.cc \
pkgsrc/emulators/gxemul/patches/patch-src_machines_machine__landisk.cc \
pkgsrc/emulators/gxemul/patches/patch-src_machines_machine__test.cc \
pkgsrc/emulators/gxemul/patches/patch-src_main_GXemul.cc \
pkgsrc/emulators/gxemul/patches/patch-src_old__main_emul.cc \
pkgsrc/emulators/gxemul/patches/patch-src_old__main_main.cc \
pkgsrc/emulators/gxemul/patches/patch-src_old__main_memory.cc \
pkgsrc/emulators/gxemul/patches/patch-src_old__main_settings.cc \
pkgsrc/emulators/gxemul/patches/patch-src_promemul_arcbios.cc \
pkgsrc/emulators/gxemul/patches/patch-src_promemul_dec__prom.cc \
pkgsrc/emulators/gxemul/patches/patch-src_promemul_dreamcast.cc \
pkgsrc/emulators/gxemul/patches/patch-src_promemul_ps2__bios.cc \
pkgsrc/emulators/gxemul/patches/patch-src_symbol_symbol.cc
cvs rdiff -u -r0 -r1.3 \
pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__dreamcast__gdrom.cc
cvs rdiff -u -r1.2 -r1.3 \
pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__sh4.cc
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: pkgsrc/emulators/gxemul/distinfo
diff -u pkgsrc/emulators/gxemul/distinfo:1.51 pkgsrc/emulators/gxemul/distinfo:1.52
--- pkgsrc/emulators/gxemul/distinfo:1.51 Mon Sep 4 11:19:43 2017
+++ pkgsrc/emulators/gxemul/distinfo Wed Mar 21 17:39:42 2018
@@ -1,24 +1,67 @@
-$NetBSD: distinfo,v 1.51 2017/09/04 11:19:43 ryoon Exp $
+$NetBSD: distinfo,v 1.52 2018/03/21 17:39:42 kamil Exp $
SHA1 (gxemul-0.6.0.1.tar.gz) = 8a9b7a6c08628c2a59a6e7e9c7c449c3826b4744
RMD160 (gxemul-0.6.0.1.tar.gz) = 6943173d4149bfe40218715b8ed2c82b5b361e50
SHA512 (gxemul-0.6.0.1.tar.gz) = 028764c751d67bf5da02ee2c34e6607660c2044e431b06c3d6799ba4e76f605b8c02afaa5f59c3059aff6253e35149831580bb13383121fb5ac0392c12d2aec2
Size (gxemul-0.6.0.1.tar.gz) = 5420978 bytes
SHA1 (patch-aa) = 6f2c0dc94606ba213bcc73527ea4bef997c89c45
-SHA1 (patch-ad) = a8757e7397ec3cc301d02bdf93654f55d558d29f
+SHA1 (patch-ad) = 8dceff813ebf3702f8b48fb535708f1223254814
SHA1 (patch-ae) = 19ef822c16f0f6dd50aea719e0bc797c39d1f9c0
-SHA1 (patch-ag) = 00eb698213b86e84d72b9ae5ece789ec37aea1ab
+SHA1 (patch-ag) = db1c914220bf3bae6f61faba5ba9b7ed8ea995bd
SHA1 (patch-src_components_cpu_CPUDyntransComponent.cc) = 1a70375b3ed409ef43122ce7e6935c07b4ed386d
SHA1 (patch-src_components_cpu_M88K__CPUComponent.cc) = 931cdc9a806e9ff48dccb2a63873c52491336b30
SHA1 (patch-src_components_cpu_MIPS__CPUComponent.cc) = 75d8276092fcdc9f548f874e5807ae8e6a2b9eae
SHA1 (patch-src_console_console.cc) = 0b9c07eaa26a39b20a6f6769cdf02208fc9667d3
-SHA1 (patch-src_cpus_cpu_mips.cc) = d239116e4ce5e040a1bdf39b803ca9a05500be53
-SHA1 (patch-src_cpus_cpu_mips_instr.cc) = be40f86a103d2366d13a884d957848d4f680dc61
+SHA1 (patch-src_console_x11.cc) = e1efce66afa230310615453fc6f8427b00c33b08
+SHA1 (patch-src_cpus_cpu.cc) = c882bc71844588e83e172b693142b1c725f86d17
+SHA1 (patch-src_cpus_cpu__alpha.cc) = 1ef38e5930018f310220efb0bf7f357fd5a9af7b
+SHA1 (patch-src_cpus_cpu__alpha__palcode.cc) = ae892bb7191e199329952feeb544fe31bd5407e2
+SHA1 (patch-src_cpus_cpu__dyntrans.cc) = d3887e19e1a153cc16fd38422e24efab8bfb672e
+SHA1 (patch-src_cpus_cpu__m88k.cc) = b21d57f101ef6c7275a70c2052ce089fb6a256c5
+SHA1 (patch-src_cpus_cpu__m88k__instr.cc) = 35fc38cb5a4efedf15e22be25196c39e817aeeb8
+SHA1 (patch-src_cpus_cpu__m88k__instr__loadstore.cc) = f4837cd03c47eb980d4ca815e9dc953eaa13ca6c
+SHA1 (patch-src_cpus_cpu__ppc.cc) = 013a6a6ea28acc1ba1751813b5dfa3d11d251427
+SHA1 (patch-src_cpus_cpu__ppc__instr.cc) = cdc664f35cdb289380bb959f1b07c95151b60eed
+SHA1 (patch-src_cpus_cpu__sh.cc) = b72eb6b670fad93198c9ee7d1bb57c0a69027a3a
+SHA1 (patch-src_cpus_cpu_mips.cc) = 0fdeed0a52b4b8a2e256e0f1084cf5a2131a6dce
+SHA1 (patch-src_cpus_cpu_mips_instr.cc) = 5166ef06cbacfd8ecb73796da6d7c511ed42728d
+SHA1 (patch-src_cpus_memory__alpha.cc) = 9bea508cc59aa6856928f0d6f5964f5f24ac648e
+SHA1 (patch-src_cpus_memory__mips__v2p.cc) = 2b859ffa219ded4e7c4a6a0ad3047e4c444d472d
+SHA1 (patch-src_cpus_memory__ppc.cc) = e321cc7acaa4a61fda91f46b05f10863d407ae9f
+SHA1 (patch-src_cpus_memory__sh.cc) = a13b3da5acd134a9145186b8294eec19ce4f6c37
+SHA1 (patch-src_debugger_debugger.cc) = c37a93845d0b77350a22c793d84da4a05342423a
+SHA1 (patch-src_debugger_debugger__cmds.cc) = cc02739c1561b4b1e8e503bcdd8a7fcfa183f5b2
+SHA1 (patch-src_devices_bus__pci.cc) = 5a4b7360a8701055d92d22489c777884338f1f38
+SHA1 (patch-src_devices_dev__algor.cc) = 0d841679b1f230dfd52fe02836f9ff544e78cf21
+SHA1 (patch-src_devices_dev__dreamcast__gdrom.cc) = 673fbb19f530486cb64a14ac941f62db493b0900
+SHA1 (patch-src_devices_dev__dreamcast__maple.cc) = 933917c91b9dcbd2f97090760477525c3ee044a8
SHA1 (patch-src_devices_dev__footbridge.cc) = 2dc76e65fff7e6c846d9d06b74bed76075b0c79a
-SHA1 (patch-src_devices_dev__sh4.cc) = fffd194470bbe830369c814595e0bea968f43809
+SHA1 (patch-src_devices_dev__lca.cc) = 3dadd75e3c561b300c0d9fc1aff086da92c2c1ae
+SHA1 (patch-src_devices_dev__pvr.cc) = 8444baf6379ed8b4c6b2fe8943dc7f808b195981
+SHA1 (patch-src_devices_dev__sgi__mardigras.cc) = 2585bc8e0117a36e214364e5ff875754f250fae9
+SHA1 (patch-src_devices_dev__sh4.cc) = 83ab4cc46a96721da9472f392f8e91a26ee557a7
+SHA1 (patch-src_devices_dev__vga.cc) = b7e889f7ecec48ff446a2d64fe0587118de8aa21
+SHA1 (patch-src_devices_dev__vr41xx.cc) = 5daf48f57a9f16d695f913341e92944816dbf062
+SHA1 (patch-src_devices_dev__wdc.cc) = 38038c02aab576c3574a1cb468f6e7bbefe5f5da
+SHA1 (patch-src_disk_bootblock.cc) = 11dd3135cb433ced29972fe28e18568025beaf82
+SHA1 (patch-src_disk_diskimage.cc) = 05f077314ee76cd0fd77582d5b725be491a42857
+SHA1 (patch-src_file_file__elf.cc) = be7e20bfca2d10e2f7fdbf0289483416d21dec3e
+SHA1 (patch-src_file_file__raw.cc) = 9c34c96cca79b795554d307cd134334ae0eb568c
SHA1 (patch-src_include_components_CPUDyntransComponent.h) = 4fa3c327c4ce5ee9e39e7bc49ce6029b2a7da100
SHA1 (patch-src_include_components_M88K__CPUComponent.h) = afd07ae4df33d0c0a9d3d8c15dca4ef9ee7dd916
SHA1 (patch-src_include_components_MIPS__CPUComponent.h) = 4e49da9af0d220a1ea7c4520d8e7e53d8d84c155
SHA1 (patch-src_include_mips_cpu_types.h) = ae5fcfa68596f4705fc07434fcd95a3ac6205763
SHA1 (patch-src_include_refcount__ptr.h) = 8021524ff16d3a9de65bb6188fb8c07296c5c3b7
-SHA1 (patch-src_machines_machine__pmax.cc) = 19b97031837f9fa911b02d624f824834ce8c0e89
+SHA1 (patch-src_machines_machine__landisk.cc) = ec3fd4916ab6092fb004e03e711653dbc20f5fc0
+SHA1 (patch-src_machines_machine__pmax.cc) = d556a834cd656d53a5aa851d5e89f655935aeb95
+SHA1 (patch-src_machines_machine__test.cc) = fbb54c473d77d4fe6bfb3cd01b72113991f77dc5
+SHA1 (patch-src_main_GXemul.cc) = a4ce4bd37347eaffc03216e27667fe636d35de29
+SHA1 (patch-src_old__main_emul.cc) = c8ef84dbed5adba7ee95dcc030ec190ffa002e67
+SHA1 (patch-src_old__main_main.cc) = ad0c6ca2712e69b4813eb6b712cd80033be04b7c
+SHA1 (patch-src_old__main_memory.cc) = 247ddf938a270b5069e45aca84ae36fe1a252124
+SHA1 (patch-src_old__main_settings.cc) = 759498320709b693088a177d9d264895306c825d
+SHA1 (patch-src_promemul_arcbios.cc) = 07881593bb29cc125ebaa1e424ed1fa80c52babf
+SHA1 (patch-src_promemul_dec__prom.cc) = 31b2e001784cbb15a838a1a42576c2935b44ca7c
+SHA1 (patch-src_promemul_dreamcast.cc) = eed1c7a713918ce782cf4c717758980038c8c065
+SHA1 (patch-src_promemul_ps2__bios.cc) = 17b4a27b61e588481e063c0ac509b55ad28a1127
+SHA1 (patch-src_symbol_symbol.cc) = 4edc42207d7c4af193b55fd4d9e03eee4180a7b2
Index: pkgsrc/emulators/gxemul/patches/patch-ad
diff -u pkgsrc/emulators/gxemul/patches/patch-ad:1.1 pkgsrc/emulators/gxemul/patches/patch-ad:1.2
--- pkgsrc/emulators/gxemul/patches/patch-ad:1.1 Sun Jul 17 12:49:17 2011
+++ pkgsrc/emulators/gxemul/patches/patch-ad Wed Mar 21 17:39:42 2018
@@ -1,12 +1,42 @@
-$NetBSD: patch-ad,v 1.1 2011/07/17 12:49:17 mrg Exp $
+$NetBSD: patch-ad,v 1.2 2018/03/21 17:39:42 kamil Exp $
patch to fix big-endian mips support from matt%netbsd.org@localhost
-
+Fix C++11 literals.
diff -rup src/cpus/cpu_mips_coproc.cc src/cpus/cpu_mips_coproc.cc
---- src/cpus/cpu_mips_coproc.cc 2009-06-21 09:03:48.000000000 -0700
-+++ src/cpus/cpu_mips_coproc.cc 2009-11-12 12:22:12.000000000 -0800
-@@ -1987,6 +1987,13 @@ void coproc_function(struct cpu *cpu, st
+--- src/cpus/cpu_mips_coproc.cc.orig 2014-08-17 08:45:15.000000000 +0000
++++ src/cpus/cpu_mips_coproc.cc
+@@ -1628,19 +1628,19 @@ void coproc_tlbwri(struct cpu *cpu, int
+ /* Debug dump of the previous entry at that index: */
+ fatal("{ old TLB entry at index %02x:", index);
+ if (cpu->cd.mips.cpu_type.mmu_model == MMU3K) {
+- fatal(" hi=%08"PRIx32, (uint32_t)cp->tlbs[index].hi);
+- fatal(" lo=%08"PRIx32, (uint32_t)cp->tlbs[index].lo0);
++ fatal(" hi=%08" PRIx32, (uint32_t)cp->tlbs[index].hi);
++ fatal(" lo=%08" PRIx32, (uint32_t)cp->tlbs[index].lo0);
+ } else {
+ if (cpu->is_32bit) {
+- fatal(" mask=%08"PRIx32,(uint32_t)cp->tlbs[index].mask);
+- fatal(" hi=%08"PRIx32, (uint32_t)cp->tlbs[index].hi);
+- fatal(" lo0=%08"PRIx32, (uint32_t)cp->tlbs[index].lo0);
+- fatal(" lo1=%08"PRIx32, (uint32_t)cp->tlbs[index].lo1);
++ fatal(" mask=%08" PRIx32,(uint32_t)cp->tlbs[index].mask);
++ fatal(" hi=%08" PRIx32, (uint32_t)cp->tlbs[index].hi);
++ fatal(" lo0=%08" PRIx32, (uint32_t)cp->tlbs[index].lo0);
++ fatal(" lo1=%08" PRIx32, (uint32_t)cp->tlbs[index].lo1);
+ } else {
+- fatal(" mask=%016"PRIx64, cp->tlbs[index].mask);
+- fatal(" hi=%016"PRIx64, cp->tlbs[index].hi);
+- fatal(" lo0=%016"PRIx64, cp->tlbs[index].lo0);
+- fatal(" lo1=%016"PRIx64, cp->tlbs[index].lo1);
++ fatal(" mask=%016" PRIx64, cp->tlbs[index].mask);
++ fatal(" hi=%016" PRIx64, cp->tlbs[index].hi);
++ fatal(" lo0=%016" PRIx64, cp->tlbs[index].lo0);
++ fatal(" lo1=%016" PRIx64, cp->tlbs[index].lo1);
+ }
+ }
+ fatal(" }\n");
+@@ -1993,6 +1993,13 @@ void coproc_function(struct cpu *cpu, st
if (cpnr < 2 && (((function & 0x03e007f8) == (COPz_MTCz << 21))
|| ((function & 0x03e007f8) == (COPz_DMTCz << 21)))) {
@@ -20,7 +50,7 @@ diff -rup src/cpus/cpu_mips_coproc.cc sr
if (unassemble_only) {
debug("%s%i\t%s,", copz==COPz_DMTCz? "dmtc" : "mtc",
cpnr, regnames[rt]);
-@@ -1996,16 +2003,10 @@ void coproc_function(struct cpu *cpu, st
+@@ -2002,16 +2009,10 @@ void coproc_function(struct cpu *cpu, st
debug("r%i", rd);
if (function & 7)
debug(",%i", (int)(function & 7));
@@ -38,3 +68,16 @@ diff -rup src/cpus/cpu_mips_coproc.cc sr
coproc_register_write(cpu, cpu->cd.mips.coproc[cpnr], rd,
&tmpvalue, copz == COPz_DMTCz, function & 7);
return;
+@@ -2225,10 +2226,9 @@ void coproc_function(struct cpu *cpu, st
+ return;
+ }
+
+- fatal("cpu%i: UNIMPLEMENTED coproc%i function %08"PRIx32" "
+- "(pc = %016"PRIx64")\n", cpu->cpu_id, cp->coproc_nr,
++ fatal("cpu%i: UNIMPLEMENTED coproc%i function %08" PRIx32 " "
++ "(pc = %016" PRIx64 ")\n", cpu->cpu_id, cp->coproc_nr,
+ (uint32_t)function, cpu->pc);
+
+ mips_cpu_exception(cpu, EXCEPTION_CPU, 0, 0, cp->coproc_nr, 0, 0, 0);
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu_mips.cc
diff -u pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu_mips.cc:1.1 pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu_mips.cc:1.2
--- pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu_mips.cc:1.1 Tue Mar 29 19:03:07 2016
+++ pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu_mips.cc Wed Mar 21 17:39:42 2018
@@ -1,10 +1,168 @@
-$NetBSD: patch-src_cpus_cpu_mips.cc,v 1.1 2016/03/29 19:03:07 mrg Exp $
+$NetBSD: patch-src_cpus_cpu_mips.cc,v 1.2 2018/03/21 17:39:42 kamil Exp $
implement trap with immediate instructions present in MIPS32.
---- src/cpus/cpu_mips.cc.orig 2014-08-17 01:45:15.000000000 -0700
-+++ src/cpus/cpu_mips.cc 2016-03-28 11:51:05.000000000 -0700
-@@ -1457,6 +1457,12 @@
+Fix C++11 literals.
+
+--- src/cpus/cpu_mips.cc.orig 2014-08-17 08:45:15.000000000 +0000
++++ src/cpus/cpu_mips.cc
+@@ -514,13 +514,13 @@ void mips_cpu_tlbdump(struct machine *m,
+ (int) cop0->reg[COP0_INDEX],
+ (int) cop0->reg[COP0_RANDOM]);
+ else
+- printf("index=0x%016"PRIx64
+- " random=0x%016"PRIx64,
++ printf("index=0x%016" PRIx64
++ " random=0x%016" PRIx64,
+ (uint64_t) cop0->reg[COP0_INDEX],
+ (uint64_t) cop0->reg[COP0_RANDOM]);
+
+ if (m->cpus[i]->cd.mips.cpu_type.isa_level >= 3)
+- printf(" wired=0x%"PRIx64,
++ printf(" wired=0x%" PRIx64,
+ (uint64_t) cop0->reg[COP0_WIRED]);
+
+ printf(")\n");
+@@ -529,22 +529,22 @@ void mips_cpu_tlbdump(struct machine *m,
+ nr_of_tlb_entries; j++) {
+ if (m->cpus[i]->cd.mips.cpu_type.mmu_model ==
+ MMU3K)
+- printf("%3i: hi=0x%08"PRIx32" lo=0x%08"
+- PRIx32"\n", j,
++ printf("%3i: hi=0x%08" PRIx32 " lo=0x%08"
++ PRIx32 "\n", j,
+ (uint32_t) cop0->tlbs[j].hi,
+ (uint32_t) cop0->tlbs[j].lo0);
+ else if (m->cpus[i]->is_32bit)
+- printf("%3i: hi=0x%08"PRIx32" mask=0x"
+- "%08"PRIx32" lo0=0x%08"PRIx32
+- " lo1=0x%08"PRIx32"\n", j,
++ printf("%3i: hi=0x%08" PRIx32 " mask=0x"
++ "%08" PRIx32 " lo0=0x%08" PRIx32
++ " lo1=0x%08" PRIx32 "\n", j,
+ (uint32_t) cop0->tlbs[j].hi,
+ (uint32_t) cop0->tlbs[j].mask,
+ (uint32_t) cop0->tlbs[j].lo0,
+ (uint32_t) cop0->tlbs[j].lo1);
+ else
+- printf("%3i: hi=0x%016"PRIx64" mask="
+- "0x%016"PRIx64" lo0=0x%016"PRIx64
+- " lo1=0x%016"PRIx64"\n", j,
++ printf("%3i: hi=0x%016" PRIx64 " mask="
++ "0x%016" PRIx64 " lo0=0x%016" PRIx64
++ " lo1=0x%016" PRIx64 "\n", j,
+ (uint64_t) cop0->tlbs[j].hi,
+ (uint64_t) cop0->tlbs[j].mask,
+ (uint64_t) cop0->tlbs[j].lo0,
+@@ -579,7 +579,7 @@ void mips_cpu_tlbdump(struct machine *m,
+ default:printf("index=0x%x random=0x%x",
+ (int) (cop0->reg[COP0_INDEX] & INDEX_MASK),
+ (int) (cop0->reg[COP0_RANDOM] & RANDOM_MASK));
+- printf(" wired=0x%"PRIx64,
++ printf(" wired=0x%" PRIx64,
+ (uint64_t) cop0->reg[COP0_WIRED]);
+ }
+
+@@ -622,11 +622,11 @@ void mips_cpu_tlbdump(struct machine *m,
+ break;
+ default:switch (m->cpus[i]->cd.mips.cpu_type.mmu_model){
+ case MMU32:
+- printf("vaddr=0x%08"PRIx32" ",
++ printf("vaddr=0x%08" PRIx32 " ",
+ (uint32_t) (hi & ~mask));
+ break;
+ default:/* R4x00, R1x000, MIPS64, etc. */
+- printf("vaddr=%016"PRIx64" ",
++ printf("vaddr=%016" PRIx64 " ",
+ (uint64_t) (hi & ~mask));
+ }
+ if (hi & TLB_G)
+@@ -644,7 +644,7 @@ void mips_cpu_tlbdump(struct machine *m,
+ paddr >>= ENTRYLO_PFN_SHIFT;
+ paddr <<= pageshift;
+ paddr &= ~(mask >> 1);
+- printf(" p0=0x%09"PRIx64" ",
++ printf(" p0=0x%09" PRIx64 " ",
+ (uint64_t) paddr);
+ }
+ printf(lo0 & ENTRYLO_D? "D" : " ");
+@@ -656,7 +656,7 @@ void mips_cpu_tlbdump(struct machine *m,
+ paddr >>= ENTRYLO_PFN_SHIFT;
+ paddr <<= pageshift;
+ paddr &= ~(mask >> 1);
+- printf(" p1=0x%09"PRIx64" ",
++ printf(" p1=0x%09" PRIx64 " ",
+ (uint64_t) paddr);
+ }
+ printf(lo1 & ENTRYLO_D? "D" : " ");
+@@ -718,9 +718,9 @@ int mips_cpu_disassemble_instr(struct cp
+ debug("cpu%i: ", cpu->cpu_id);
+
+ if (cpu->is_32bit)
+- debug("%08"PRIx32, (uint32_t)dumpaddr);
++ debug("%08" PRIx32, (uint32_t)dumpaddr);
+ else
+- debug("%016"PRIx64, (uint64_t)dumpaddr);
++ debug("%016" PRIx64, (uint64_t)dumpaddr);
+
+ memcpy(instr, originstr, sizeof(uint32_t));
+
+@@ -1008,9 +1008,9 @@ int mips_cpu_disassemble_instr(struct cp
+ }
+
+ if (cpu->is_32bit)
+- debug("0x%08"PRIx32, (uint32_t)addr);
++ debug("0x%08" PRIx32, (uint32_t)addr);
+ else
+- debug("0x%016"PRIx64, (uint64_t)addr);
++ debug("0x%016" PRIx64, (uint64_t)addr);
+
+ symbol = get_symbol_name(&cpu->machine->symbol_context,
+ addr, &offset);
+@@ -1187,7 +1187,7 @@ int mips_cpu_disassemble_instr(struct cp
+ rt, imm, regnames[rs]);
+
+ if (running) {
+- debug("\t[0x%016"PRIx64" = %s]",
++ debug("\t[0x%016" PRIx64 " = %s]",
+ (uint64_t)(cpu->cd.mips.gpr[rs] + imm));
+ if (symbol != NULL)
+ debug(" = %s", symbol);
+@@ -1212,10 +1212,10 @@ int mips_cpu_disassemble_instr(struct cp
+ debug("\t[");
+
+ if (cpu->is_32bit)
+- debug("0x%08"PRIx32,
++ debug("0x%08" PRIx32,
+ (uint32_t) (cpu->cd.mips.gpr[rs] + imm));
+ else
+- debug("0x%016"PRIx64,
++ debug("0x%016" PRIx64,
+ (uint64_t) (cpu->cd.mips.gpr[rs] + imm));
+
+ if (symbol != NULL)
+@@ -1239,9 +1239,9 @@ int mips_cpu_disassemble_instr(struct cp
+ addr, &offset);
+ debug("%s\t0x", hi6_names[hi6]);
+ if (cpu->is_32bit)
+- debug("%08"PRIx32, (uint32_t) addr);
++ debug("%08" PRIx32, (uint32_t) addr);
+ else
+- debug("%016"PRIx64, (uint64_t) addr);
++ debug("%016" PRIx64, (uint64_t) addr);
+ if (symbol != NULL)
+ debug("\t<%s>", symbol);
+ break;
+@@ -1281,7 +1281,7 @@ int mips_cpu_disassemble_instr(struct cp
+ if (cache_op==6) debug("hit writeback");
+ if (cache_op==7) debug("hit set virtual");
+ if (running)
+- debug(", addr 0x%016"PRIx64,
++ debug(", addr 0x%016" PRIx64,
+ (uint64_t)(cpu->cd.mips.gpr[rt] + imm));
+ if (showtag)
+ debug(", taghi=%08lx lo=%08lx",
+@@ -1457,14 +1457,20 @@ int mips_cpu_disassemble_instr(struct cp
case REGIMM_BLTZALL:
case REGIMM_BGEZAL:
case REGIMM_BGEZALL:
@@ -17,3 +175,164 @@ implement trap with immediate instructio
debug("%s\t%s,", regimm_names[regimm5], regnames[rs]);
addr = (dumpaddr + 4) + (imm << 2);
+
+ if (cpu->is_32bit)
+- debug("0x%08"PRIx32, (uint32_t) addr);
++ debug("0x%08" PRIx32, (uint32_t) addr);
+ else
+- debug("0x%016"PRIx64, (uint64_t) addr);
++ debug("0x%016" PRIx64, (uint64_t) addr);
+ break;
+
+ case REGIMM_SYNCI:
+@@ -1509,30 +1515,30 @@ void mips_cpu_register_dump(struct cpu *
+ cpu->pc, &offset);
+
+ if (bits32)
+- debug("cpu%i: pc = %08"PRIx32,
++ debug("cpu%i: pc = %08" PRIx32,
+ cpu->cpu_id, (uint32_t) cpu->pc);
+ else if (bits128)
+- debug("cpu%i: pc=%016"PRIx64,
++ debug("cpu%i: pc=%016" PRIx64,
+ cpu->cpu_id, (uint64_t) cpu->pc);
+ else
+- debug("cpu%i: pc = 0x%016"PRIx64,
++ debug("cpu%i: pc = 0x%016" PRIx64,
+ cpu->cpu_id, (uint64_t) cpu->pc);
+
+ debug(" <%s>\n", symbol != NULL? symbol :
+ " no symbol ");
+
+ if (bits32)
+- debug("cpu%i: hi = %08"PRIx32" lo = %08"PRIx32"\n",
++ debug("cpu%i: hi = %08" PRIx32 " lo = %08" PRIx32 "\n",
+ cpu->cpu_id, (uint32_t) cpu->cd.mips.hi,
+ (uint32_t) cpu->cd.mips.lo);
+ else if (bits128) {
+- debug("cpu%i: hi=%016"PRIx64"%016"PRIx64" lo="
+- "%016"PRIx64"%016"PRIx64"\n", cpu->cpu_id,
++ debug("cpu%i: hi=%016" PRIx64 "%016" PRIx64 " lo="
++ "%016" PRIx64 "%016" PRIx64 "\n", cpu->cpu_id,
+ cpu->cd.mips.hi1, cpu->cd.mips.hi,
+ cpu->cd.mips.lo1, cpu->cd.mips.lo);
+ } else {
+- debug("cpu%i: hi = 0x%016"PRIx64" lo = 0x%016"
+- PRIx64"\n", cpu->cpu_id,
++ debug("cpu%i: hi = 0x%016" PRIx64 " lo = 0x%016"
++ PRIx64 "\n", cpu->cpu_id,
+ (uint64_t) cpu->cd.mips.hi,
+ (uint64_t) cpu->cd.mips.lo);
+ }
+@@ -1548,7 +1554,7 @@ void mips_cpu_register_dump(struct cpu *
+ debug(" "
+ " ");
+ else
+- debug(" %3s=%016"PRIx64"%016"PRIx64,
++ debug(" %3s=%016" PRIx64 "%016" PRIx64,
+ regnames[r], (uint64_t)
+ cpu->cd.mips.gpr_quadhi[r],
+ (uint64_t)cpu->cd.mips.gpr[r]);
+@@ -1563,7 +1569,7 @@ void mips_cpu_register_dump(struct cpu *
+ if (i == MIPS_GPR_ZERO)
+ debug(" ");
+ else
+- debug(" %3s = %08"PRIx32, regnames[i],
++ debug(" %3s = %08" PRIx32, regnames[i],
+ (uint32_t)cpu->cd.mips.gpr[i]);
+ if ((i & 3) == 3)
+ debug("\n");
+@@ -1577,7 +1583,7 @@ void mips_cpu_register_dump(struct cpu *
+ if (r == MIPS_GPR_ZERO)
+ debug(" ");
+ else
+- debug(" %3s = 0x%016"PRIx64,
++ debug(" %3s = 0x%016" PRIx64,
+ regnames[r],
+ (uint64_t)cpu->cd.mips.gpr[r]);
+ if ((i & 1) == 1)
+@@ -1622,7 +1628,7 @@ void mips_cpu_register_dump(struct cpu *
+ (int) cpu->cd.mips.coproc[
+ coprocnr]->reg[i]);
+ else
+- debug(" = 0x%016"PRIx64, (uint64_t)
++ debug(" = 0x%016" PRIx64, (uint64_t)
+ cpu->cd.mips.coproc[
+ coprocnr]->reg[i]);
+ }
+@@ -1640,10 +1646,10 @@ void mips_cpu_register_dump(struct cpu *
+ debug("cpu%i: ", cpu->cpu_id);
+ debug("config_select1 = 0x");
+ if (cpu->is_32bit)
+- debug("%08"PRIx32,
++ debug("%08" PRIx32,
+ (uint32_t)cpu->cd.mips.cop0_config_select1);
+ else
+- debug("%016"PRIx64,
++ debug("%016" PRIx64,
+ (uint64_t)cpu->cd.mips.cop0_config_select1);
+ debug("\n");
+ }
+@@ -1673,7 +1679,7 @@ void mips_cpu_register_dump(struct cpu *
+
+ if (cpu->cd.mips.rmw) {
+ printf("cpu%i: Read-Modify-Write in progress, address "
+- "0x%016"PRIx64"\n", cpu->cpu_id, cpu->cd.mips.rmw_addr);
++ "0x%016" PRIx64 "\n", cpu->cpu_id, cpu->cd.mips.rmw_addr);
+ }
+ }
+
+@@ -1764,10 +1770,10 @@ void mips_cpu_exception(struct cpu *cpu,
+ d, strbuf, sizeof(strbuf)));
+ } else {
+ if (cpu->is_32bit)
+- debug(" a%i=0x%"PRIx32, x,
++ debug(" a%i=0x%" PRIx32, x,
+ (uint32_t)d);
+ else
+- debug(" a%i=0x%"PRIx64, x,
++ debug(" a%i=0x%" PRIx64, x,
+ (uint64_t)d);
+ }
+ }
+@@ -1781,13 +1787,13 @@ void mips_cpu_exception(struct cpu *cpu,
+ if (cpu->is_32bit)
+ debug(" vaddr=0x%08x", (int)vaddr);
+ else
+- debug(" vaddr=0x%016"PRIx64, (uint64_t)vaddr);
++ debug(" vaddr=0x%016" PRIx64, (uint64_t)vaddr);
+ }
+
+ if (cpu->is_32bit)
+- debug(" pc=0x%08"PRIx32" ", (uint32_t)cpu->pc);
++ debug(" pc=0x%08" PRIx32" ", (uint32_t)cpu->pc);
+ else
+- debug(" pc=0x%016"PRIx64" ", (uint64_t)cpu->pc);
++ debug(" pc=0x%016" PRIx64" ", (uint64_t)cpu->pc);
+
+ if (symbol != NULL)
+ debug("<%s> ]\n", symbol);
+@@ -1804,14 +1810,14 @@ void mips_cpu_exception(struct cpu *cpu,
+ fatal("cpu%i: ", cpu->cpu_id);
+ fatal("warning: LOW reference: vaddr=");
+ if (cpu->is_32bit)
+- fatal("0x%08"PRIx32, (uint32_t) vaddr);
++ fatal("0x%08" PRIx32, (uint32_t) vaddr);
+ else
+- fatal("0x%016"PRIx64, (uint64_t) vaddr);
++ fatal("0x%016" PRIx64, (uint64_t) vaddr);
+ fatal(", exception %s, pc=", exception_names[exccode]);
+ if (cpu->is_32bit)
+- fatal("0x%08"PRIx32, (uint32_t) cpu->pc);
++ fatal("0x%08" PRIx32, (uint32_t) cpu->pc);
+ else
+- fatal("0x%016"PRIx64, (uint64_t)cpu->pc);
++ fatal("0x%016" PRIx64, (uint64_t)cpu->pc);
+ fatal(" <%s> ]\n", symbol? symbol : "(no symbol)");
+ }
+
+@@ -1974,4 +1980,3 @@ void mips_cpu_exception(struct cpu *cpu,
+
+
+ #include "tmp_mips_tail.cc"
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu_mips_instr.cc
diff -u pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu_mips_instr.cc:1.1 pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu_mips_instr.cc:1.2
--- pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu_mips_instr.cc:1.1 Tue Mar 29 19:03:07 2016
+++ pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu_mips_instr.cc Wed Mar 21 17:39:42 2018
@@ -1,10 +1,12 @@
-$NetBSD: patch-src_cpus_cpu_mips_instr.cc,v 1.1 2016/03/29 19:03:07 mrg Exp $
+$NetBSD: patch-src_cpus_cpu_mips_instr.cc,v 1.2 2018/03/21 17:39:42 kamil Exp $
implement trap with immediate instructions present in MIPS32.
---- src/cpus/cpu_mips_instr.cc.orig 2016-03-28 11:59:41.000000000 -0700
-+++ src/cpus/cpu_mips_instr.cc 2016-03-28 12:04:07.000000000 -0700
-@@ -1461,6 +1461,92 @@
+Fix C++11 literals.
+
+--- src/cpus/cpu_mips_instr.cc.orig 2014-08-17 08:45:15.000000000 +0000
++++ src/cpus/cpu_mips_instr.cc
+@@ -1461,6 +1461,92 @@ X(tne)
}
}
@@ -97,7 +99,16 @@ implement trap with immediate instructio
/*
* 3-register arithmetic instructions:
-@@ -4446,6 +4532,37 @@
+@@ -3983,7 +4069,7 @@ X(to_be_translated)
+ if (cpu->delay_slot) {
+ if (!cpu->translation_readahead)
+ fatal("TODO: branch in delay slot (=%i)? (3);"
+- " addr=%016"PRIx64" iword=%08"PRIx32"\n",
++ " addr=%016" PRIx64 " iword=%08" PRIx32 "\n",
+ cpu->delay_slot, (uint64_t)addr, iword);
+ goto bad;
+ }
+@@ -4446,6 +4532,37 @@ X(to_be_translated)
}
break;
@@ -135,3 +146,17 @@ implement trap with immediate instructio
default:if (!cpu->translation_readahead)
fatal("UNIMPLEMENTED regimm rt=%i\n", rt);
goto bad;
+@@ -4753,7 +4870,7 @@ X(to_be_translated)
+ if (!has_warned && !cpu->translation_readahead) {
+ fatal("[ WARNING/NOTE: attempt to execute a 64-bit"
+ " instruction on an emulated 32-bit processor; "
+- "pc=0x%08"PRIx32" ]\n", (uint32_t)cpu->pc);
++ "pc=0x%08" PRIx32 " ]\n", (uint32_t)cpu->pc);
+ has_warned = 1;
+ }
+ if (cpu->translation_readahead)
+@@ -4770,4 +4887,3 @@ X(to_be_translated)
+ #include "cpu_dyntrans.cc"
+ #undef DYNTRANS_TO_BE_TRANSLATED_TAIL
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_machines_machine__pmax.cc
diff -u pkgsrc/emulators/gxemul/patches/patch-src_machines_machine__pmax.cc:1.1 pkgsrc/emulators/gxemul/patches/patch-src_machines_machine__pmax.cc:1.2
--- pkgsrc/emulators/gxemul/patches/patch-src_machines_machine__pmax.cc:1.1 Thu Jun 29 17:51:46 2017
+++ pkgsrc/emulators/gxemul/patches/patch-src_machines_machine__pmax.cc Wed Mar 21 17:39:42 2018
@@ -1,10 +1,21 @@
-$NetBSD: patch-src_machines_machine__pmax.cc,v 1.1 2017/06/29 17:51:46 christos Exp $
+$NetBSD: patch-src_machines_machine__pmax.cc,v 1.2 2018/03/21 17:39:42 kamil Exp $
sd0 -> rz0 so we can find our boot device.
---- src/machines/machine_pmax.cc.orig 2017-06-29 13:46:24.964078725 -0400
-+++ src/machines/machine_pmax.cc 2017-06-29 13:46:39.643612752 -0400
-@@ -789,7 +789,7 @@
+Fix C++11 literals.
+
+--- src/machines/machine_pmax.cc.orig 2014-08-17 08:45:14.000000000 +0000
++++ src/machines/machine_pmax.cc
+@@ -660,7 +660,7 @@ abort();
+
+ /* KN230 mainbus / interrupt controller: */
+ snprintf(tmpstr, sizeof(tmpstr),
+- "kn230 addr=0x%"PRIx64, (uint64_t) KN230_SYS_ICSR);
++ "kn230 addr=0x%" PRIx64, (uint64_t) KN230_SYS_ICSR);
+ device_add(machine, tmpstr);
+
+ /*
+@@ -789,7 +789,7 @@ abort();
strlcpy(bootpath, "rz(0,0,0)", sizeof(bootpath));
else
#endif
@@ -13,3 +24,34 @@ sd0 -> rz0 so we can find our boot devic
if (machine->bootdev_id < 0 || machine->force_netboot) {
/* tftp boot: */
+@@ -885,7 +885,7 @@ abort();
+ */
+ {
+ char tmps[300];
+- snprintf(tmps, sizeof(tmps), "cca=%"PRIx32,
++ snprintf(tmps, sizeof(tmps), "cca=%" PRIx32,
+ (uint32_t) (DEC_DECCCA_BASEADDR + 0xa0000000ULL));
+ add_environment_string(cpu, tmps, &addr);
+ }
+@@ -898,14 +898,14 @@ abort();
+ tmps[sizeof(tmps)-1] = '\0';
+ add_environment_string(cpu, tmps, &addr);
+
+- snprintf(tmps, sizeof(tmps), "bitmap=0x%"PRIx32, (uint32_t)
++ snprintf(tmps, sizeof(tmps), "bitmap=0x%" PRIx32, (uint32_t)
+ ( (DEC_MEMMAP_ADDR + sizeof(uint32_t) /* skip the
+ page size and point to the memmap */
+ ) & 0xffffffffULL) );
+ tmps[sizeof(tmps)-1] = '\0';
+ add_environment_string(cpu, tmps, &addr);
+
+- snprintf(tmps, sizeof(tmps), "bitmaplen=0x%"PRIx32, (uint32_t)
++ snprintf(tmps, sizeof(tmps), "bitmaplen=0x%" PRIx32, (uint32_t)
+ ( machine->physical_ram_in_mb * 1048576 / 4096 / 8) );
+ tmps[sizeof(tmps)-1] = '\0';
+ add_environment_string(cpu, tmps, &addr);
+@@ -994,4 +994,3 @@ MACHINE_REGISTER(pmax)
+
+ me->set_default_ram = machine_default_ram_pmax;
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-ag
diff -u pkgsrc/emulators/gxemul/patches/patch-ag:1.4 pkgsrc/emulators/gxemul/patches/patch-ag:1.5
--- pkgsrc/emulators/gxemul/patches/patch-ag:1.4 Thu May 11 12:38:30 2017
+++ pkgsrc/emulators/gxemul/patches/patch-ag Wed Mar 21 17:39:42 2018
@@ -1,12 +1,31 @@
-$NetBSD: patch-ag,v 1.4 2017/05/11 12:38:30 christos Exp $
+$NetBSD: patch-ag,v 1.5 2018/03/21 17:39:42 kamil Exp $
- enable all CPSR->SPSR copy values, instead of hard coding 3 out of 15.
- allow immediate to be zero with a non-zero shift. caused by:
ebf61a60: e28fc600 add ip,pc,#0
+- Fix C++11 literals.
---- src/cpus/cpu_arm_instr.cc.orig 2014-08-17 04:45:15.000000000 -0400
-+++ src/cpus/cpu_arm_instr.cc 2017-05-11 08:36:16.634585212 -0400
-@@ -2670,6 +2670,7 @@
+--- src/cpus/cpu_arm_instr.cc.orig 2014-08-17 08:45:15.000000000 +0000
++++ src/cpus/cpu_arm_instr.cc
+@@ -215,7 +215,7 @@ X(invalid) {
+
+ fatal("FATAL ERROR: An internal error occured in the ARM"
+ " dyntrans code. Please contact the author with detailed"
+- " repro steps on how to trigger this bug. pc = 0x%08"PRIx32"\n",
++ " repro steps on how to trigger this bug. pc = 0x%08" PRIx32 "\n",
+ (uint32_t)cpu->pc);
+
+ cpu->cd.arm.next_ic = ¬hing_call;
+@@ -803,7 +803,7 @@ X(msr_imm_spsr)
+ cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1) << ARM_INSTR_ALIGNMENT_SHIFT);
+ cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
+ old_pc = cpu->pc;
+- printf("msr_spsr: old pc = 0x%08"PRIx32"\n", old_pc);
++ printf("msr_spsr: old pc = 0x%08" PRIx32 "\n", old_pc);
+ }
+ exit(1);
+ }
+@@ -2670,6 +2670,7 @@ X(to_be_translated)
ic->f = cond_instr(bx);
}
ic->arg[0] = (size_t)(&cpu->cd.arm.r[rm]);
@@ -14,7 +33,7 @@ $NetBSD: patch-ag,v 1.4 2017/05/11 12:38
break;
}
if ((iword & 0x0fb00ff0) == 0x1000090) {
-@@ -2888,7 +2889,7 @@
+@@ -2888,7 +2889,7 @@ X(to_be_translated)
while (r8-- > 0)
imm = (imm >> 2) | ((imm & 3) << 30);
@@ -23,3 +42,8 @@ $NetBSD: patch-ag,v 1.4 2017/05/11 12:38
if (!cpu->translation_readahead)
fatal("TODO: see cpu_arm_instr_dpi; non-zero steps but still under 256 is not implemented yet\n");
goto bad;
+@@ -3205,4 +3206,3 @@ okay:
+ #include "cpu_dyntrans.cc"
+ #undef DYNTRANS_TO_BE_TRANSLATED_TAIL
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__sh4.cc
diff -u pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__sh4.cc:1.2 pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__sh4.cc:1.3
--- pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__sh4.cc:1.2 Sun Jul 16 16:36:09 2017
+++ pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__sh4.cc Wed Mar 21 17:39:42 2018
@@ -1,10 +1,114 @@
-$NetBSD: patch-src_devices_dev__sh4.cc,v 1.2 2017/07/16 16:36:09 christos Exp $
+$NetBSD: patch-src_devices_dev__sh4.cc,v 1.3 2018/03/21 17:39:42 kamil Exp $
Put the actual number of characters waiting in the FIFO instead of 1 or 0
---- src/devices/dev_sh4.cc.orig 2014-08-17 04:45:12.000000000 -0400
-+++ src/devices/dev_sh4.cc 2017-07-16 09:58:19.288954403 -0400
-@@ -1703,8 +1703,8 @@
+Fix C++11 literals.
+
+--- src/devices/dev_sh4.cc.orig 2014-08-17 08:45:12.000000000 +0000
++++ src/devices/dev_sh4.cc
+@@ -844,7 +844,7 @@ DEVICE_ACCESS(sh4_pcic)
+ /* Hardcoded to what OpenBSD/landisk uses: */
+ if (writeflag == MEM_WRITE && idata != 0xac000000) {
+ fatal("sh4_pcic: SH4_PCICONF5 unknown value"
+- " 0x%"PRIx32"\n", (uint32_t) idata);
++ " 0x%" PRIx32 "\n", (uint32_t) idata);
+ exit(1);
+ }
+ break;
+@@ -853,7 +853,7 @@ DEVICE_ACCESS(sh4_pcic)
+ /* Hardcoded to what OpenBSD/landisk uses: */
+ if (writeflag == MEM_WRITE && idata != 0x8c000000) {
+ fatal("sh4_pcic: SH4_PCICONF6 unknown value"
+- " 0x%"PRIx32"\n", (uint32_t) idata);
++ " 0x%" PRIx32 "\n", (uint32_t) idata);
+ exit(1);
+ }
+ break;
+@@ -862,7 +862,7 @@ DEVICE_ACCESS(sh4_pcic)
+ /* Hardcoded to what OpenBSD/landisk uses: */
+ if (writeflag == MEM_WRITE && idata != ((64 - 1) << 20)) {
+ fatal("sh4_pcic: SH4_PCILSR0 unknown value"
+- " 0x%"PRIx32"\n", (uint32_t) idata);
++ " 0x%" PRIx32 "\n", (uint32_t) idata);
+ exit(1);
+ }
+ break;
+@@ -871,7 +871,7 @@ DEVICE_ACCESS(sh4_pcic)
+ /* Hardcoded to what OpenBSD/landisk uses: */
+ if (writeflag == MEM_WRITE && idata != 0xac000000) {
+ fatal("sh4_pcic: SH4_PCILAR0 unknown value"
+- " 0x%"PRIx32"\n", (uint32_t) idata);
++ " 0x%" PRIx32 "\n", (uint32_t) idata);
+ exit(1);
+ }
+ break;
+@@ -880,7 +880,7 @@ DEVICE_ACCESS(sh4_pcic)
+ /* Hardcoded to what OpenBSD/landisk uses: */
+ if (writeflag == MEM_WRITE && idata != ((64 - 1) << 20)) {
+ fatal("sh4_pcic: SH4_PCILSR1 unknown value"
+- " 0x%"PRIx32"\n", (uint32_t) idata);
++ " 0x%" PRIx32 "\n", (uint32_t) idata);
+ exit(1);
+ }
+ break;
+@@ -889,15 +889,15 @@ DEVICE_ACCESS(sh4_pcic)
+ /* Hardcoded to what OpenBSD/landisk uses: */
+ if (writeflag == MEM_WRITE && idata != 0xac000000) {
+ fatal("sh4_pcic: SH4_PCILAR1 unknown value"
+- " 0x%"PRIx32"\n", (uint32_t) idata);
++ " 0x%" PRIx32 "\n", (uint32_t) idata);
+ exit(1);
+ }
+ break;
+
+ case SH4_PCIMBR:
+ if (writeflag == MEM_WRITE && idata != SH4_PCIC_MEM) {
+- fatal("sh4_pcic: PCIMBR set to 0x%"PRIx32", not"
+- " 0x%"PRIx32"? TODO\n", (uint32_t) idata,
++ fatal("sh4_pcic: PCIMBR set to 0x%" PRIx32 ", not"
++ " 0x%" PRIx32 "? TODO\n", (uint32_t) idata,
+ (uint32_t) SH4_PCIC_MEM);
+ exit(1);
+ }
+@@ -905,8 +905,8 @@ DEVICE_ACCESS(sh4_pcic)
+
+ case SH4_PCIIOBR:
+ if (writeflag == MEM_WRITE && idata != SH4_PCIC_IO) {
+- fatal("sh4_pcic: PCIIOBR set to 0x%"PRIx32", not"
+- " 0x%"PRIx32"? TODO\n", (uint32_t) idata,
++ fatal("sh4_pcic: PCIIOBR set to 0x%" PRIx32 ", not"
++ " 0x%" PRIx32 "? TODO\n", (uint32_t) idata,
+ (uint32_t) SH4_PCIC_IO);
+ exit(1);
+ }
+@@ -982,7 +982,7 @@ DEVICE_ACCESS(sh4)
+ d->sdmr3 = v;
+ else
+ d->sdmr2 = v;
+- debug("[ sh4: sdmr%i set to 0x%04"PRIx16" ]\n",
++ debug("[ sh4: sdmr%i set to 0x%04" PRIx16 " ]\n",
+ relative_addr & 0x00040000? 3 : 2, v);
+ return 1;
+ }
+@@ -1235,7 +1235,7 @@ DEVICE_ACCESS(sh4)
+ if (idata & (TCR_ICPF | TCR_ICPE1 | TCR_ICPE0 |
+ TCR_CKEG1 | TCR_CKEG0 | TCR_TPSC2)) {
+ fatal("Unimplemented SH4 timer control"
+- " bits: 0x%08"PRIx32". Aborting.\n",
++ " bits: 0x%08" PRIx32 ". Aborting.\n",
+ (int) idata);
+ exit(1);
+ }
+@@ -1299,7 +1299,7 @@ DEVICE_ACCESS(sh4)
+ if (idata & ~0x00ffffff) {
+ fatal("[ SH4 DMA: Attempt to set top 8 "
+ "bits of the count register? 0x%08"
+- PRIx32" ]\n", (uint32_t) idata);
++ PRIx32 " ]\n", (uint32_t) idata);
+ exit(1);
+ }
+
+@@ -1703,8 +1703,8 @@ DEVICE_ACCESS(sh4)
case SH4_SCIF_BASE + SCIF_FDR:
/* Nr of bytes in the TX and RX fifos, respectively: */
@@ -15,3 +119,8 @@ Put the actual number of characters wait
break;
case SH4_SCIF_BASE + SCIF_SPTR:
+@@ -2000,4 +2000,3 @@ DEVINIT(sh4)
+
+ return 1;
+ }
+-
Added files:
Index: pkgsrc/emulators/gxemul/patches/patch-src_console_x11.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_console_x11.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_console_x11.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,15 @@
+$NetBSD: patch-src_console_x11.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/console/x11.cc.orig 2014-08-17 08:45:15.000000000 +0000
++++ src/console/x11.cc
+@@ -374,7 +374,7 @@ void x11_fb_resize(struct fb_window *win
+ void x11_set_standard_properties(struct fb_window *fb_window, char *name)
+ {
+ XSetStandardProperties(fb_window->x11_display,
+- fb_window->x11_fb_window, name, "GXemul "VERSION,
++ fb_window->x11_fb_window, name, "GXemul " VERSION,
+ None, NULL, 0, NULL);
+ }
+
Index: pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,60 @@
+$NetBSD: patch-src_cpus_cpu.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/cpus/cpu.cc.orig 2014-08-17 08:45:15.000000000 +0000
++++ src/cpus/cpu.cc
+@@ -245,9 +245,9 @@ void cpu_functioncall_trace(struct cpu *
+ fatal("%s", symbol);
+ else {
+ if (cpu->is_32bit)
+- fatal("0x%"PRIx32, (uint32_t) f);
++ fatal("0x%" PRIx32, (uint32_t) f);
+ else
+- fatal("0x%"PRIx64, (uint64_t) f);
++ fatal("0x%" PRIx64, (uint64_t) f);
+ }
+ fatal("(");
+
+@@ -258,7 +258,7 @@ void cpu_functioncall_trace(struct cpu *
+
+ #ifdef PRINT_MEMORY_CHECKSUM
+ /* Temporary hack for finding bugs: */
+- fatal("call chksum=%016"PRIx64"\n", memory_checksum(cpu->mem));
++ fatal("call chksum=%016" PRIx64 "\n", memory_checksum(cpu->mem));
+ #endif
+ }
+
+@@ -425,7 +425,7 @@ void cpu_show_cycles(struct machine *mac
+ if (!machine->show_nr_of_instructions && !forced)
+ goto do_return;
+
+- printf("[ %"PRIi64" instrs", (int64_t) cpu->ninstrs);
++ printf("[ %" PRIi64 " instrs", (int64_t) cpu->ninstrs);
+
+ /* Instructions per second, and average so far: */
+ is = 1000 * (ninstrs-ninstrs_last) / (mseconds-mseconds_last);
+@@ -439,15 +439,15 @@ void cpu_show_cycles(struct machine *mac
+ printf("; idling");
+ cpu->has_been_idling = 0;
+ } else
+- printf("; i/s=%"PRIi64" avg=%"PRIi64, is, avg);
++ printf("; i/s=%" PRIi64 " avg=%" PRIi64, is, avg);
+
+ symbol = get_symbol_name(&machine->symbol_context, pc, &offset);
+
+ if (machine->ncpus == 1) {
+ if (cpu->is_32bit)
+- printf("; pc=0x%08"PRIx32, (uint32_t) pc);
++ printf("; pc=0x%08" PRIx32, (uint32_t) pc);
+ else
+- printf("; pc=0x%016"PRIx64, (uint64_t) pc);
++ printf("; pc=0x%016" PRIx64, (uint64_t) pc);
+ }
+
+ /* Special hack for M88K userland: (Don't show symbols.) */
+@@ -568,4 +568,3 @@ void cpu_init(void)
+ {
+ ADD_ALL_CPU_FAMILIES;
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__alpha.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__alpha.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__alpha.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,64 @@
+$NetBSD: patch-src_cpus_cpu__alpha.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/cpus/cpu_alpha.cc.orig 2014-08-17 08:45:15.000000000 +0000
++++ src/cpus/cpu_alpha.cc
+@@ -181,14 +181,14 @@ void alpha_cpu_register_dump(struct cpu
+ if (gprs) {
+ symbol = get_symbol_name(&cpu->machine->symbol_context,
+ cpu->pc, &offset);
+- debug("cpu%i:\t pc = 0x%016"PRIx64, x, (uint64_t) cpu->pc);
++ debug("cpu%i:\t pc = 0x%016" PRIx64, x, (uint64_t) cpu->pc);
+ debug(" <%s>\n", symbol != NULL? symbol : " no symbol ");
+ for (i=0; i<N_ALPHA_REGS; i++) {
+ int r = (i >> 1) + ((i & 1) << 4);
+ if ((i % 2) == 0)
+ debug("cpu%i:\t", x);
+ if (r != ALPHA_ZERO)
+- debug("%3s = 0x%016"PRIx64, alpha_regname[r],
++ debug("%3s = 0x%016" PRIx64, alpha_regname[r],
+ (uint64_t) cpu->cd.alpha.r[r]);
+ if ((i % 2) == 1)
+ debug("\n");
+@@ -283,7 +283,7 @@ int alpha_cpu_disassemble_instr(struct c
+ if (cpu->machine->ncpus > 1 && running)
+ debug("cpu%i:\t", cpu->cpu_id);
+
+- debug("%016"PRIx64": ", (uint64_t) dumpaddr);
++ debug("%016" PRIx64 ": ", (uint64_t) dumpaddr);
+
+ iw = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24);
+ debug("%08x\t", (int)iw);
+@@ -594,7 +594,7 @@ int alpha_cpu_disassemble_instr(struct c
+ debug("jsr");
+ debug("\t%s,", alpha_regname[ra]);
+ debug("(%s),", alpha_regname[rb]);
+- debug("0x%"PRIx64, (uint64_t) tmp);
++ debug("0x%" PRIx64, (uint64_t) tmp);
+ symbol = get_symbol_name(&cpu->machine->symbol_context,
+ tmp, &offset);
+ if (symbol != NULL)
+@@ -616,7 +616,7 @@ int alpha_cpu_disassemble_instr(struct c
+ debug("%s\t", opcode==0x30? "br" : "bsr");
+ if (ra != ALPHA_ZERO)
+ debug("%s,", alpha_regname[ra]);
+- debug("0x%"PRIx64, (uint64_t) tmp);
++ debug("0x%" PRIx64, (uint64_t) tmp);
+ symbol = get_symbol_name(&cpu->machine->symbol_context,
+ tmp, &offset);
+ if (symbol != NULL)
+@@ -656,7 +656,7 @@ int alpha_cpu_disassemble_instr(struct c
+ debug("f%i,", ra);
+ else
+ debug("%s,", alpha_regname[ra]);
+- debug("0x%"PRIx64, (uint64_t) tmp);
++ debug("0x%" PRIx64, (uint64_t) tmp);
+ symbol = get_symbol_name(&cpu->machine->symbol_context,
+ tmp, &offset);
+ if (symbol != NULL)
+@@ -680,4 +680,3 @@ int alpha_cpu_disassemble_instr(struct c
+
+
+ #include "tmp_alpha_tail.cc"
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__alpha__palcode.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__alpha__palcode.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__alpha__palcode.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,38 @@
+$NetBSD: patch-src_cpus_cpu__alpha__palcode.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/cpus/cpu_alpha_palcode.cc.orig 2014-08-17 08:45:15.000000000 +0000
++++ src/cpus/cpu_alpha_palcode.cc
+@@ -90,7 +90,7 @@ void alpha_palcode_name(uint32_t palcode
+ case 0xaa: snprintf(buf, buflen, "PAL_gentrap"); break;
+ case 0xae: snprintf(buf, buflen, "PAL_clrfen"); break;
+ case 0x3fffffe: snprintf(buf, buflen, "GXemul_PROM"); break;
+- default:snprintf(buf, buflen, "UNKNOWN 0x%"PRIx32, palcode);
++ default:snprintf(buf, buflen, "UNKNOWN 0x%" PRIx32, palcode);
+ }
+ }
+
+@@ -144,7 +144,7 @@ void alpha_prom_call(struct cpu *cpu)
+ store_buf(cpu, a2, s, len);
+ break;
+
+- default:fatal("[ Alpha PALcode: GXemul PROM call, a0=0x%"PRIx64" ]\n",
++ default:fatal("[ Alpha PALcode: GXemul PROM call, a0=0x%" PRIx64 " ]\n",
+ (uint64_t) cpu->cd.alpha.r[ALPHA_A0]);
+ cpu->running = 0;
+ }
+@@ -307,7 +307,7 @@ Make sure they are correct, as documente
+ * a0 = -1: invalidate everything with ASM=0.
+ * a0 = -2: invalidate everything
+ */
+- // debug("[ Alpha PALcode: PAL_OSF1_tbi: a0=%"PRIi64" a1=0x%"
++ // debug("[ Alpha PALcode: PAL_OSF1_tbi: a0=%" PRIi64 " a1=0x%"
+ // PRIx64" ]\n", (int64_t)a0, (uint64_t)a1);
+ if (a0 >= 1)
+ cpu->invalidate_translation_caches(cpu, a1, INVALIDATE_VADDR);
+@@ -390,4 +390,3 @@ Make sure they are correct, as documente
+ * However, it's easier to just leave the registers as they are.
+ */
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__dyntrans.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__dyntrans.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__dyntrans.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,166 @@
+$NetBSD: patch-src_cpus_cpu__dyntrans.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/cpus/cpu_dyntrans.cc.orig 2014-08-17 08:45:15.000000000 +0000
++++ src/cpus/cpu_dyntrans.cc
+@@ -79,10 +79,10 @@ static void gather_statistics(struct cpu
+ a += low_pc << DYNTRANS_INSTR_ALIGNMENT_SHIFT;
+ if (cpu->is_32bit)
+ snprintf(buf + strlen(buf), sizeof(buf),
+- "0x%08"PRIx32, (uint32_t)a);
++ "0x%08" PRIx32, (uint32_t)a);
+ else
+ snprintf(buf + strlen(buf), sizeof(buf),
+- "0x%016"PRIx64, (uint64_t)a);
++ "0x%016" PRIx64, (uint64_t)a);
+ break;
+ case 'v':
+ /* Virtual program counter address: */
+@@ -92,10 +92,10 @@ static void gather_statistics(struct cpu
+ a += low_pc << DYNTRANS_INSTR_ALIGNMENT_SHIFT;
+ if (cpu->is_32bit)
+ snprintf(buf + strlen(buf), sizeof(buf),
+- "0x%08"PRIx32, (uint32_t)a);
++ "0x%08" PRIx32, (uint32_t)a);
+ else
+ snprintf(buf + strlen(buf), sizeof(buf),
+- "0x%016"PRIx64, (uint64_t)a);
++ "0x%016" PRIx64, (uint64_t)a);
+ break;
+ }
+ i++;
+@@ -141,7 +141,7 @@ static void gather_statistics(struct cpu
+ cpu->pc &= ~((DYNTRANS_IC_ENTRIES_PER_PAGE-1) << \
+ DYNTRANS_INSTR_ALIGNMENT_SHIFT); \
+ cpu->pc += (low_pc << DYNTRANS_INSTR_ALIGNMENT_SHIFT);\
+- printf("Crash at %016"PRIx64"\n", cpu->pc); \
++ printf("Crash at %016" PRIx64 "\n", cpu->pc); \
+ printf("nr of I calls: %lli\n", nr_of_I_calls); \
+ printf("Next ic = %p\n", cpu->cd. \
+ DYNTRANS_ARCH.next_ic); \
+@@ -533,9 +533,9 @@ void DYNTRANS_FUNCTION_TRACE_DEF(struct
+ fatal("&%s", symbol);
+ else {
+ if (cpu->is_32bit)
+- fatal("0x%"PRIx32, (uint32_t)d);
++ fatal("0x%" PRIx32, (uint32_t)d);
+ else
+- fatal("0x%"PRIx64, (uint64_t)d);
++ fatal("0x%" PRIx64, (uint64_t)d);
+ }
+
+ if (x < n_args_to_print - 1)
+@@ -612,7 +612,7 @@ void DYNTRANS_PC_TO_POINTERS_GENERIC(str
+ x1 = (cached_pc >> (64-DYNTRANS_L1N)) & mask1;
+ x2 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
+ x3 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
+- /* fatal("X3: cached_pc=%016"PRIx64" x1=%x x2=%x x3=%x\n",
++ /* fatal("X3: cached_pc=%016" PRIx64 " x1=%x x2=%x x3=%x\n",
+ (uint64_t)cached_pc, (int)x1, (int)x2, (int)x3); */
+ l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
+ /* fatal(" l2 = %p\n", l2); */
+@@ -657,8 +657,8 @@ void DYNTRANS_PC_TO_POINTERS_GENERIC(str
+ * exception handler.
+ */
+ /* fatal("TODO: instruction vaddr=>paddr translation "
+- "failed. vaddr=0x%"PRIx64"\n", (uint64_t)cached_pc);
+- fatal("!! cpu->pc=0x%"PRIx64"\n", (uint64_t)cpu->pc); */
++ "failed. vaddr=0x%" PRIx64 "\n", (uint64_t)cached_pc);
++ fatal("!! cpu->pc=0x%" PRIx64 "\n", (uint64_t)cpu->pc); */
+
+ /* If there was an exception, the PC has changed.
+ Update cached_pc: */
+@@ -691,7 +691,7 @@ void DYNTRANS_PC_TO_POINTERS_GENERIC(str
+
+ /* printf("EXCEPTION HANDLER: vaddr = 0x%x ==> "
+ "paddr = 0x%x\n", (int)cpu->pc, (int)paddr);
+- fatal("!? cpu->pc=0x%"PRIx64"\n", (uint64_t)cpu->pc); */
++ fatal("!? cpu->pc=0x%" PRIx64 "\n", (uint64_t)cpu->pc); */
+
+ if (!ok) {
+ fatal("FATAL: could not find physical"
+@@ -754,7 +754,7 @@ void DYNTRANS_PC_TO_POINTERS_GENERIC(str
+ if (physpage_ofs == 0) {
+ uint32_t previous_first_page_in_chain;
+
+- /* fatal("CREATING page %lli (physaddr 0x%"PRIx64"), table "
++ /* fatal("CREATING page %lli (physaddr 0x%" PRIx64 "), table "
+ "index %i\n", (long long)pagenr, (uint64_t)physaddr,
+ (int)table_index); */
+
+@@ -799,8 +799,8 @@ void DYNTRANS_PC_TO_POINTERS_GENERIC(str
+ cpu->cd.DYNTRANS_ARCH.next_ic = cpu->cd.DYNTRANS_ARCH.cur_ic_page +
+ DYNTRANS_PC_TO_IC_ENTRY(cached_pc);
+
+- /* printf("cached_pc=0x%016"PRIx64" pagenr=%lli table_index=%lli, "
+- "physpage_ofs=0x%016"PRIx64"\n", (uint64_t)cached_pc, (long long)
++ /* printf("cached_pc=0x%016" PRIx64 " pagenr=%lli table_index=%lli, "
++ "physpage_ofs=0x%016" PRIx64 "\n", (uint64_t)cached_pc, (long long)
+ pagenr, (long long)table_index, (uint64_t)physpage_ofs); */
+ }
+
+@@ -861,8 +861,8 @@ have_it:
+ cpu->cd.DYNTRANS_ARCH.next_ic = cpu->cd.DYNTRANS_ARCH.cur_ic_page +
+ DYNTRANS_PC_TO_IC_ENTRY(cached_pc);
+
+- /* printf("cached_pc=0x%016"PRIx64" pagenr=%lli table_index=%lli, "
+- "physpage_ofs=0x%016"PRIx64"\n", (uint64_t)cached_pc, (long long)
++ /* printf("cached_pc=0x%016" PRIx64 " pagenr=%lli table_index=%lli, "
++ "physpage_ofs=0x%016" PRIx64 "\n", (uint64_t)cached_pc, (long long)
+ pagenr, (long long)table_index, (uint64_t)physpage_ofs); */
+ }
+ #endif /* DYNTRANS_PC_TO_POINTERS_FUNC */
+@@ -1439,8 +1439,8 @@ void DYNTRANS_UPDATE_TRANSLATION_TABLE(s
+ vaddr_page &= 0xffffffffULL;
+
+ if (paddr_page > 0xffffffffULL) {
+- fatal("update_translation_table(): v=0x%016"PRIx64", h=%p w=%i"
+- " p=0x%016"PRIx64"\n", vaddr_page, host_page, writeflag,
++ fatal("update_translation_table(): v=0x%016" PRIx64 ", h=%p w=%i"
++ " p=0x%016" PRIx64 "\n", vaddr_page, host_page, writeflag,
+ paddr_page);
+ exit(1);
+ }
+@@ -1456,8 +1456,8 @@ void DYNTRANS_UPDATE_TRANSLATION_TABLE(s
+ struct DYNTRANS_L2_64_TABLE *l2;
+ struct DYNTRANS_L3_64_TABLE *l3;
+
+- /* fatal("update_translation_table(): v=0x%016"PRIx64", h=%p w=%i"
+- " p=0x%016"PRIx64"\n", (uint64_t)vaddr_page, host_page, writeflag,
++ /* fatal("update_translation_table(): v=0x%016" PRIx64 ", h=%p w=%i"
++ " p=0x%016" PRIx64 "\n", (uint64_t)vaddr_page, host_page, writeflag,
+ (uint64_t)paddr_page); */
+ #endif
+
+@@ -1730,11 +1730,11 @@ cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].v
+ quiet_mode = tmp_old_quiet_mode;
+ }
+ #ifdef MODE32
+- fatal("BREAKPOINT: pc = 0x%"PRIx32"\n(The "
++ fatal("BREAKPOINT: pc = 0x%" PRIx32 "\n(The "
+ "instruction has not yet executed.)\n",
+ (uint32_t)cpu->pc);
+ #else
+- fatal("BREAKPOINT: pc = 0x%"PRIx64"\n(The "
++ fatal("BREAKPOINT: pc = 0x%" PRIx64 "\n(The "
+ "instruction has not yet executed.)\n",
+ (uint64_t)cpu->pc);
+ #endif
+@@ -1894,9 +1894,9 @@ bad: /*
+
+ if (cpu->machine->instruction_trace) {
+ if (cpu->is_32bit)
+- fatal(" at 0x%"PRIx32"\n", (uint32_t)cpu->pc);
++ fatal(" at 0x%" PRIx32 "\n", (uint32_t)cpu->pc);
+ else
+- fatal(" at 0x%"PRIx64"\n", (uint64_t)cpu->pc);
++ fatal(" at 0x%" PRIx64 "\n", (uint64_t)cpu->pc);
+ } else {
+ fatal(":\n");
+ DISASSEMBLE(cpu, ib, 1, 0);
+@@ -1923,4 +1923,3 @@ stop_running_translated:
+ ic->f(cpu, ic);
+
+ #endif /* DYNTRANS_TO_BE_TRANSLATED_TAIL */
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__m88k.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__m88k.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__m88k.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,191 @@
+$NetBSD: patch-src_cpus_cpu__m88k.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/cpus/cpu_m88k.cc.orig 2014-08-17 08:45:15.000000000 +0000
++++ src/cpus/cpu_m88k.cc
+@@ -278,7 +278,7 @@ void m88k_cpu_register_dump(struct cpu *
+ if (gprs) {
+ symbol = get_symbol_name(&cpu->machine->symbol_context,
+ cpu->pc, &offset);
+- debug("cpu%i: pc = 0x%08"PRIx32, x, (uint32_t)cpu->pc);
++ debug("cpu%i: pc = 0x%08" PRIx32, x, (uint32_t)cpu->pc);
+ debug(" <%s>\n", symbol != NULL? symbol : " no symbol ");
+
+ for (i=0; i<N_M88K_REGS; i++) {
+@@ -287,7 +287,7 @@ void m88k_cpu_register_dump(struct cpu *
+ if (i == 0)
+ debug(" ");
+ else
+- debug(" r%-2i = 0x%08"PRIx32,
++ debug(" r%-2i = 0x%08" PRIx32,
+ i, cpu->cd.m88k.r[i]);
+ if ((i % 4) == 3)
+ debug("\n");
+@@ -304,7 +304,7 @@ void m88k_cpu_register_dump(struct cpu *
+ for (i=0; i<n_control_regs; i++) {
+ if ((i % 4) == 0)
+ debug("cpu%i:", x);
+- debug(" %4s=0x%08"PRIx32,
++ debug(" %4s=0x%08" PRIx32,
+ m88k_cr_name(cpu, i), cpu->cd.m88k.cr[i]);
+ if ((i % 4) == 3)
+ debug("\n");
+@@ -317,7 +317,7 @@ void m88k_cpu_register_dump(struct cpu *
+ for (i=0; i<n_fpu_control_regs; i++) {
+ if ((i % 4) == 0)
+ debug("cpu%i:", x);
+- debug(" %5s=0x%08"PRIx32,
++ debug(" %5s=0x%08" PRIx32,
+ m88k_fcr_name(cpu, i), cpu->cd.m88k.fcr[i]);
+ if ((i % 4) == 3)
+ debug("\n");
+@@ -357,8 +357,8 @@ void m88k_cpu_tlbdump(struct machine *m,
+ for (i = 0; i < N_M88200_BATC_REGS; i++) {
+ uint32_t b = cmmu->batc[i];
+ printf("cpu%i: BATC[%2i]: ", cpu_nr, i);
+- printf("v=0x%08"PRIx32, b & 0xfff80000);
+- printf(", p=0x%08"PRIx32,
++ printf("v=0x%08" PRIx32, b & 0xfff80000);
++ printf(", p=0x%08" PRIx32,
+ (b << 13) & 0xfff80000);
+ printf(", %s %s %s %s %s %s\n",
+ b & BATC_SO? "SP " : "!sp",
+@@ -379,8 +379,8 @@ void m88k_cpu_tlbdump(struct machine *m,
+ printf("superv");
+ else
+ printf("user ");
+- printf(" v=0x%08"PRIx32, v & 0xfffff000);
+- printf(", p=0x%08"PRIx32, p & 0xfffff000);
++ printf(" v=0x%08" PRIx32, v & 0xfffff000);
++ printf(", p=0x%08" PRIx32, p & 0xfffff000);
+
+ printf(" %s %s %s %s %s %s %s",
+ v & PG_U1? "U1 " : "!u1",
+@@ -633,8 +633,8 @@ static void m88k_memory_transaction_debu
+ }
+ debug("bytebits=0x%x ]\n", DMT_ENBITS(dmt));
+
+- debug("[ DMD%i: 0x%08"PRIx32"; ", n, cpu->cd.m88k.dmd[n]);
+- debug("DMA%i: 0x%08"PRIx32" ]\n", n, cpu->cd.m88k.dma[n]);
++ debug("[ DMD%i: 0x%08" PRIx32 "; ", n, cpu->cd.m88k.dmd[n]);
++ debug("DMA%i: 0x%08" PRIx32 " ]\n", n, cpu->cd.m88k.dma[n]);
+ } else
+ debug("not valid ]\n");
+ }
+@@ -852,7 +852,7 @@ int m88k_cpu_disassemble_instr(struct cp
+ if (cpu->machine->ncpus > 1 && running)
+ debug("cpu%i:\t", cpu->cpu_id);
+
+- debug("%c%08"PRIx32": ",
++ debug("%c%08" PRIx32 ": ",
+ cpu->cd.m88k.cr[M88K_CR_PSR] & M88K_PSR_MODE? 's' : 'u',
+ (uint32_t) dumpaddr);
+
+@@ -861,7 +861,7 @@ int m88k_cpu_disassemble_instr(struct cp
+ else
+ iw = ib[3] + (ib[2]<<8) + (ib[1]<<16) + (ib[0]<<24);
+
+- debug("%08"PRIx32, (uint32_t) iw);
++ debug("%08" PRIx32, (uint32_t) iw);
+
+ if (running && cpu->delay_slot)
+ debug(" (d)");
+@@ -914,23 +914,23 @@ int m88k_cpu_disassemble_instr(struct cp
+ if (symbol != NULL && supervisor)
+ debug("\t; [<%s>]", symbol);
+ else
+- debug("\t; [0x%08"PRIx32"]", tmpaddr);
++ debug("\t; [0x%08" PRIx32 "]", tmpaddr);
+ if (op26 >= 0x08) {
+ /* Store: */
+ debug(" = ");
+ switch (op26 & 3) {
+- case 0: debug("0x%016"PRIx64, (uint64_t)
++ case 0: debug("0x%016" PRIx64, (uint64_t)
+ ((((uint64_t) cpu->cd.m88k.r[d])
+ << 32) + ((uint64_t)
+ cpu->cd.m88k.r[d+1])) );
+ break;
+- case 1: debug("0x%08"PRIx32,
++ case 1: debug("0x%08" PRIx32,
+ (uint32_t) cpu->cd.m88k.r[d]);
+ break;
+- case 2: debug("0x%04"PRIx16,
++ case 2: debug("0x%04" PRIx16,
+ (uint16_t) cpu->cd.m88k.r[d]);
+ break;
+- case 3: debug("0x%02"PRIx8,
++ case 3: debug("0x%02" PRIx8,
+ (uint8_t) cpu->cd.m88k.r[d]);
+ break;
+ }
+@@ -967,7 +967,7 @@ int m88k_cpu_disassemble_instr(struct cp
+ if (symbol != NULL && supervisor)
+ debug("\t; [<%s>]", symbol);
+ else
+- debug("\t; [0x%08"PRIx32"]", tmpaddr);
++ debug("\t; [0x%08" PRIx32 "]", tmpaddr);
+ }
+ }
+ debug("\n");
+@@ -1023,7 +1023,7 @@ int m88k_cpu_disassemble_instr(struct cp
+ if (symbol != NULL && supervisor)
+ debug("<%s>", symbol);
+ else
+- debug("0x%08"PRIx32, tmpaddr);
++ debug("0x%08" PRIx32, tmpaddr);
+ }
+ }
+
+@@ -1145,7 +1145,7 @@ int m88k_cpu_disassemble_instr(struct cp
+ debug("b%sr%s\t",
+ op26 >= 0x32? "s" : "",
+ op26 & 1? ".n" : "");
+- debug("0x%08"PRIx32, (uint32_t) (dumpaddr + d26));
++ debug("0x%08" PRIx32, (uint32_t) (dumpaddr + d26));
+ symbol = get_symbol_name(&cpu->machine->symbol_context,
+ dumpaddr + d26, &offset);
+ if (symbol != NULL && supervisor)
+@@ -1184,7 +1184,7 @@ int m88k_cpu_disassemble_instr(struct cp
+ } else {
+ debug("%i", d);
+ }
+- debug(",r%i,0x%08"PRIx32, s1, (uint32_t) (dumpaddr + d16));
++ debug(",r%i,0x%08" PRIx32, s1, (uint32_t) (dumpaddr + d16));
+ symbol = get_symbol_name(&cpu->machine->symbol_context,
+ dumpaddr + d16, &offset);
+ if (symbol != NULL && supervisor)
+@@ -1225,7 +1225,7 @@ int m88k_cpu_disassemble_instr(struct cp
+ if (symbol != NULL && supervisor)
+ debug("\t; [<%s>]", symbol);
+ else
+- debug("\t; [0x%08"PRIx32"]", tmpaddr);
++ debug("\t; [0x%08" PRIx32 "]", tmpaddr);
+ }
+
+ debug("\n");
+@@ -1314,7 +1314,7 @@ int m88k_cpu_disassemble_instr(struct cp
+ if (symbol != NULL && supervisor)
+ debug("\t; [<%s>]", symbol);
+ else
+- debug("\t; [0x%08"PRIx32"]", tmpaddr);
++ debug("\t; [0x%08" PRIx32 "]", tmpaddr);
+ }
+
+ debug("\n");
+@@ -1410,7 +1410,7 @@ int m88k_cpu_disassemble_instr(struct cp
+ if (symbol != NULL && supervisor)
+ debug("<%s>", symbol);
+ else
+- debug("0x%08"PRIx32, tmpaddr);
++ debug("0x%08" PRIx32, tmpaddr);
+ }
+ debug("\n");
+ break;
+@@ -1456,5 +1456,3 @@ int m88k_cpu_disassemble_instr(struct cp
+
+
+ #include "tmp_m88k_tail.cc"
+-
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__m88k__instr.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__m88k__instr.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__m88k__instr.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,46 @@
+$NetBSD: patch-src_cpus_cpu__m88k__instr.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/cpus/cpu_m88k_instr.cc.orig 2014-08-17 08:45:15.000000000 +0000
++++ src/cpus/cpu_m88k_instr.cc
+@@ -1515,14 +1515,14 @@ X(rte)
+ return;
+ }
+
+- /* fatal("RTE: NIP=0x%08"PRIx32", FIP=0x%08"PRIx32"\n",
++ /* fatal("RTE: NIP=0x%08" PRIx32 ", FIP=0x%08" PRIx32 "\n",
+ cpu->cd.m88k.cr[M88K_CR_SNIP], cpu->cd.m88k.cr[M88K_CR_SFIP]); */
+
+ quick_pc_to_pointers(cpu);
+ return;
+
+ abort_dump:
+- fatal("RTE failed. NIP=0x%08"PRIx32", FIP=0x%08"PRIx32"\n",
++ fatal("RTE failed. NIP=0x%08" PRIx32 ", FIP=0x%08" PRIx32 "\n",
+ cpu->cd.m88k.cr[M88K_CR_SNIP], cpu->cd.m88k.cr[M88K_CR_SFIP]);
+
+ ABORT_EXECUTION;
+@@ -1833,7 +1833,7 @@ X(end_of_page2)
+ if (low_pc < 0 || low_pc > ((M88K_IC_ENTRIES_PER_PAGE+1)
+ << M88K_INSTR_ALIGNMENT_SHIFT)) {
+ printf("[ end_of_page2: HUH? low_pc=%i, cpu->pc = %08"
+- PRIx32" ]\n", low_pc, (uint32_t) cpu->pc);
++ PRIx32 " ]\n", low_pc, (uint32_t) cpu->pc);
+ }
+
+ /* This doesn't count as an executed instruction. */
+@@ -2699,7 +2699,7 @@ X(to_be_translated)
+ if (iword == 0xf400fc00)
+ ic->f = instr(rte);
+ else {
+- fatal("unimplemented rte variant: 0x%08"PRIx32"\n", iword);
++ fatal("unimplemented rte variant: 0x%08" PRIx32 "\n", iword);
+ goto bad;
+ }
+ break;
+@@ -2722,4 +2722,3 @@ X(to_be_translated)
+ #include "cpu_dyntrans.cc"
+ #undef DYNTRANS_TO_BE_TRANSLATED_TAIL
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__m88k__instr__loadstore.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__m88k__instr__loadstore.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__m88k__instr__loadstore.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,20 @@
+$NetBSD: patch-src_cpus_cpu__m88k__instr__loadstore.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/cpus/cpu_m88k_instr_loadstore.cc.orig 2014-08-17 08:45:15.000000000 +0000
++++ src/cpus/cpu_m88k_instr_loadstore.cc
+@@ -161,7 +161,7 @@ void LS_GENERIC_N(struct cpu *cpu, struc
+ m88k_exception(cpu, M88K_EXCEPTION_MISALIGNED_ACCESS, 0);
+ #else
+ fatal("{ m88k dyntrans alignment exception, size = %i,"
+- " addr = %08"PRIx32", pc = %08"PRIx32" }\n", LS_SIZE,
++ " addr = %08" PRIx32 ", pc = %08" PRIx32 " }\n", LS_SIZE,
+ (uint32_t) addr, (uint32_t) cpu->pc);
+
+ /* TODO: Generalize this into a abort_call, or similar: */
+@@ -450,4 +450,3 @@ void LS_N(struct cpu *cpu, struct m88k_i
+
+ #endif /* store */
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__ppc.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__ppc.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__ppc.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,296 @@
+$NetBSD: patch-src_cpus_cpu__ppc.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/cpus/cpu_ppc.cc.orig 2014-08-17 08:45:15.000000000 +0000
++++ src/cpus/cpu_ppc.cc
+@@ -361,7 +361,7 @@ void ppc_exception(struct cpu *cpu, int
+ cpu->cd.ppc.spr[SPR_SRR1] = (cpu->cd.ppc.msr & 0x87c0ffff);
+
+ if (!quiet_mode)
+- fatal("[ PPC Exception 0x%x; pc=0x%"PRIx64" ]\n",
++ fatal("[ PPC Exception 0x%x; pc=0x%" PRIx64 " ]\n",
+ exception_nr, cpu->pc);
+
+ /* Disable External Interrupts, Recoverable Interrupt Mode,
+@@ -401,17 +401,17 @@ void ppc_cpu_register_dump(struct cpu *c
+
+ debug("cpu%i: pc = 0x", x);
+ if (bits32)
+- debug("%08"PRIx32, (uint32_t)cpu->pc);
++ debug("%08" PRIx32, (uint32_t)cpu->pc);
+ else
+- debug("%016"PRIx64, (uint64_t)cpu->pc);
++ debug("%016" PRIx64, (uint64_t)cpu->pc);
+ debug(" <%s>\n", symbol != NULL? symbol : " no symbol ");
+
+ debug("cpu%i: lr = 0x", x);
+ if (bits32)
+- debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_LR]);
++ debug("%08" PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_LR]);
+ else
+- debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_LR]);
+- debug(" cr = 0x%08"PRIx32, (uint32_t)cpu->cd.ppc.cr);
++ debug("%016" PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_LR]);
++ debug(" cr = 0x%08" PRIx32, (uint32_t)cpu->cd.ppc.cr);
+
+ if (bits32)
+ debug(" ");
+@@ -419,15 +419,15 @@ void ppc_cpu_register_dump(struct cpu *c
+ debug("\ncpu%i: ", x);
+ debug("ctr = 0x", x);
+ if (bits32)
+- debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_CTR]);
++ debug("%08" PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_CTR]);
+ else
+- debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_CTR]);
++ debug("%016" PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_CTR]);
+
+ debug(" xer = 0x", x);
+ if (bits32)
+- debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_XER]);
++ debug("%08" PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_XER]);
+ else
+- debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_XER]);
++ debug("%016" PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_XER]);
+
+ debug("\n");
+
+@@ -436,7 +436,7 @@ void ppc_cpu_register_dump(struct cpu *c
+ for (i=0; i<PPC_NGPRS; i++) {
+ if ((i % 4) == 0)
+ debug("cpu%i:", x);
+- debug(" r%02i = 0x%08"PRIx32" ", i,
++ debug(" r%02i = 0x%08" PRIx32 " ", i,
+ (uint32_t) cpu->cd.ppc.gpr[i]);
+ if ((i % 4) == 3)
+ debug("\n");
+@@ -447,7 +447,7 @@ void ppc_cpu_register_dump(struct cpu *c
+ int r = (i >> 1) + ((i & 1) << 4);
+ if ((i % 2) == 0)
+ debug("cpu%i:", x);
+- debug(" r%02i = 0x%016"PRIx64" ", r,
++ debug(" r%02i = 0x%016" PRIx64 " ", r,
+ (uint64_t) cpu->cd.ppc.gpr[r]);
+ if ((i % 2) == 1)
+ debug("\n");
+@@ -456,13 +456,13 @@ void ppc_cpu_register_dump(struct cpu *c
+
+ /* Other special registers: */
+ if (bits32) {
+- debug("cpu%i: srr0 = 0x%08"PRIx32
+- " srr1 = 0x%08"PRIx32"\n", x,
++ debug("cpu%i: srr0 = 0x%08" PRIx32
++ " srr1 = 0x%08" PRIx32 "\n", x,
+ (uint32_t) cpu->cd.ppc.spr[SPR_SRR0],
+ (uint32_t) cpu->cd.ppc.spr[SPR_SRR1]);
+ } else {
+- debug("cpu%i: srr0 = 0x%016"PRIx64
+- " srr1 = 0x%016"PRIx64"\n", x,
++ debug("cpu%i: srr0 = 0x%016" PRIx64
++ " srr1 = 0x%016" PRIx64 "\n", x,
+ (uint64_t) cpu->cd.ppc.spr[SPR_SRR0],
+ (uint64_t) cpu->cd.ppc.spr[SPR_SRR1]);
+ }
+@@ -470,25 +470,25 @@ void ppc_cpu_register_dump(struct cpu *c
+ debug("cpu%i: msr = ", x);
+ reg_access_msr(cpu, &tmp, 0, 0);
+ if (bits32)
+- debug("0x%08"PRIx32, (uint32_t) tmp);
++ debug("0x%08" PRIx32, (uint32_t) tmp);
+ else
+- debug("0x%016"PRIx64, (uint64_t) tmp);
++ debug("0x%016" PRIx64, (uint64_t) tmp);
+
+- debug(" tb = 0x%08"PRIx32"%08"PRIx32"\n",
++ debug(" tb = 0x%08" PRIx32 "%08" PRIx32 "\n",
+ (uint32_t) cpu->cd.ppc.spr[SPR_TBU],
+ (uint32_t) cpu->cd.ppc.spr[SPR_TBL]);
+
+- debug("cpu%i: dec = 0x%08"PRIx32,
++ debug("cpu%i: dec = 0x%08" PRIx32,
+ x, (uint32_t) cpu->cd.ppc.spr[SPR_DEC]);
+ if (!bits32)
+- debug(" hdec = 0x%08"PRIx32"\n",
++ debug(" hdec = 0x%08" PRIx32 "\n",
+ (uint32_t) cpu->cd.ppc.spr[SPR_HDEC]);
+
+ debug("\n");
+ }
+
+ if (coprocs & 1) {
+- debug("cpu%i: fpscr = 0x%08"PRIx32"\n",
++ debug("cpu%i: fpscr = 0x%08" PRIx32 "\n",
+ x, (uint32_t) cpu->cd.ppc.fpscr);
+
+ /* TODO: show floating-point values :-) */
+@@ -498,7 +498,7 @@ void ppc_cpu_register_dump(struct cpu *c
+ for (i=0; i<PPC_NFPRS; i++) {
+ if ((i % 2) == 0)
+ debug("cpu%i:", x);
+- debug(" f%02i = 0x%016"PRIx64" ", i,
++ debug(" f%02i = 0x%016" PRIx64 " ", i,
+ (uint64_t) cpu->cd.ppc.fpr[i]);
+ if ((i % 2) == 1)
+ debug("\n");
+@@ -506,7 +506,7 @@ void ppc_cpu_register_dump(struct cpu *c
+ }
+
+ if (coprocs & 2) {
+- debug("cpu%i: sdr1 = 0x%"PRIx64"\n", x,
++ debug("cpu%i: sdr1 = 0x%" PRIx64 "\n", x,
+ (uint64_t) cpu->cd.ppc.spr[SPR_SDR1]);
+ if (cpu->cd.ppc.cpu_type.flags & PPC_601)
+ debug("cpu%i: PPC601-style, TODO!\n");
+@@ -517,8 +517,8 @@ void ppc_cpu_register_dump(struct cpu *c
+ uint32_t lower = cpu->cd.ppc.spr[spr+1];
+ uint32_t len = (((upper & BAT_BL) << 15)
+ | 0x1ffff) + 1;
+- debug("cpu%i: %sbat%i: u=0x%08"PRIx32
+- " l=0x%08"PRIx32" ",
++ debug("cpu%i: %sbat%i: u=0x%08" PRIx32
++ " l=0x%08" PRIx32 " ",
+ x, i<4? "i" : "d", i&3, upper, lower);
+ if (!(upper & BAT_V)) {
+ debug(" (not valid)\n");
+@@ -555,7 +555,7 @@ void ppc_cpu_register_dump(struct cpu *c
+ uint32_t s = cpu->cd.ppc.sr[i];
+
+ debug("cpu%i:", x);
+- debug(" sr%-2i = 0x%08"PRIx32, i, s);
++ debug(" sr%-2i = 0x%08" PRIx32, i, s);
+
+ s &= (SR_TYPE | SR_SUKEY | SR_PRKEY | SR_NOEXEC);
+ if (s != 0) {
+@@ -653,15 +653,15 @@ int ppc_cpu_disassemble_instr(struct cpu
+ debug("cpu%i: ", cpu->cpu_id);
+
+ if (cpu->cd.ppc.bits == 32)
+- debug("%08"PRIx32, (uint32_t) dumpaddr);
++ debug("%08" PRIx32, (uint32_t) dumpaddr);
+ else
+- debug("%016"PRIx64, (uint64_t) dumpaddr);
++ debug("%016" PRIx64, (uint64_t) dumpaddr);
+
+ /* NOTE: Fixed to big-endian. */
+ iword = (instr[0] << 24) + (instr[1] << 16) + (instr[2] << 8)
+ + instr[3];
+
+- debug(": %08"PRIx32"\t", iword);
++ debug(": %08" PRIx32 "\t", iword);
+
+ /*
+ * Decode the instruction:
+@@ -762,9 +762,9 @@ int ppc_cpu_disassemble_instr(struct cpu
+ if (cpu->cd.ppc.bits == 32)
+ addr &= 0xffffffff;
+ if (cpu->cd.ppc.bits == 32)
+- debug("0x%"PRIx32, (uint32_t) addr);
++ debug("0x%" PRIx32, (uint32_t) addr);
+ else
+- debug("0x%"PRIx64, (uint64_t) addr);
++ debug("0x%" PRIx64, (uint64_t) addr);
+ symbol = get_symbol_name(&cpu->machine->symbol_context,
+ addr, &offset);
+ if (symbol != NULL)
+@@ -795,9 +795,9 @@ int ppc_cpu_disassemble_instr(struct cpu
+ if (cpu->cd.ppc.bits == 32)
+ addr &= 0xffffffff;
+ if (cpu->cd.ppc.bits == 32)
+- debug("\t0x%"PRIx32, (uint32_t) addr);
++ debug("\t0x%" PRIx32, (uint32_t) addr);
+ else
+- debug("\t0x%"PRIx64, (uint64_t) addr);
++ debug("\t0x%" PRIx64, (uint64_t) addr);
+ symbol = get_symbol_name(&cpu->machine->symbol_context,
+ addr, &offset);
+ if (symbol != NULL)
+@@ -1086,7 +1086,7 @@ int ppc_cpu_disassemble_instr(struct cpu
+ if (symbol != NULL)
+ debug(" \t<%s", symbol);
+ else
+- debug(" \t<0x%"PRIx64, (uint64_t) addr);
++ debug(" \t<0x%" PRIx64, (uint64_t) addr);
+ if (wlen > 0 && !fpreg /* && !reverse */) {
+ /* TODO */
+ }
+@@ -1257,10 +1257,10 @@ int ppc_cpu_disassemble_instr(struct cpu
+ ppc_spr_names[spr]==NULL? "?" : ppc_spr_names[spr]);
+ if (running) {
+ if (cpu->cd.ppc.bits == 32)
+- debug(": 0x%"PRIx32, (uint32_t)
++ debug(": 0x%" PRIx32, (uint32_t)
+ cpu->cd.ppc.spr[spr]);
+ else
+- debug(": 0x%"PRIx64, (uint64_t)
++ debug(": 0x%" PRIx64, (uint64_t)
+ cpu->cd.ppc.spr[spr]);
+ }
+ debug(">");
+@@ -1417,10 +1417,10 @@ int ppc_cpu_disassemble_instr(struct cpu
+ ppc_spr_names[spr]==NULL? "?" : ppc_spr_names[spr]);
+ if (running) {
+ if (cpu->cd.ppc.bits == 32)
+- debug(": 0x%"PRIx32, (uint32_t)
++ debug(": 0x%" PRIx32, (uint32_t)
+ cpu->cd.ppc.gpr[rs]);
+ else
+- debug(": 0x%"PRIx64, (uint64_t)
++ debug(": 0x%" PRIx64, (uint64_t)
+ cpu->cd.ppc.gpr[rs]);
+ }
+ debug(">");
+@@ -1573,7 +1573,7 @@ int ppc_cpu_disassemble_instr(struct cpu
+ if (symbol != NULL)
+ debug(" \t<%s", symbol);
+ else
+- debug(" \t<0x%"PRIx64, (uint64_t) addr);
++ debug(" \t<0x%" PRIx64, (uint64_t) addr);
+ if (wlen > 0 && load && wlen > 0) {
+ unsigned char tw[8];
+ uint64_t tdata = 0;
+@@ -1597,12 +1597,12 @@ int ppc_cpu_disassemble_instr(struct cpu
+ if (symbol != NULL)
+ debug("%s", symbol);
+ else
+- debug("0x%"PRIx64,
++ debug("0x%" PRIx64,
+ (uint64_t) tdata);
+ } else {
+ /* TODO: if load==2, then this is
+ a _signed_ load. */
+- debug("0x%"PRIx64, (uint64_t) tdata);
++ debug("0x%" PRIx64, (uint64_t) tdata);
+ }
+ } else
+ debug(": unreadable");
+@@ -1620,12 +1620,12 @@ int ppc_cpu_disassemble_instr(struct cpu
+ if (symbol != NULL)
+ debug("%s", symbol);
+ else
+- debug("0x%"PRIx64, (uint64_t) tdata);
++ debug("0x%" PRIx64, (uint64_t) tdata);
+ } else {
+ if (tdata > -256 && tdata < 256)
+ debug("%i", (int)tdata);
+ else
+- debug("0x%"PRIx64, (uint64_t) tdata);
++ debug("0x%" PRIx64, (uint64_t) tdata);
+ }
+ }
+ debug(">");
+@@ -1817,7 +1817,7 @@ static void debug_spr_usage(uint64_t pc,
+ break;
+ } else
+ fatal("[ using UNIMPLEMENTED spr %i (%s), pc = "
+- "0x%"PRIx64" ]\n", spr, ppc_spr_names[spr] == NULL?
++ "0x%" PRIx64 " ]\n", spr, ppc_spr_names[spr] == NULL?
+ "UNKNOWN" : ppc_spr_names[spr], (uint64_t) pc);
+ }
+
+@@ -1862,5 +1862,3 @@ void update_cr0(struct cpu *cpu, uint64_
+
+
+ #include "tmp_ppc_tail.cc"
+-
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__ppc__instr.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__ppc__instr.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__ppc__instr.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,20 @@
+$NetBSD: patch-src_cpus_cpu__ppc__instr.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/cpus/cpu_ppc_instr.cc.orig 2014-08-17 08:45:15.000000000 +0000
++++ src/cpus/cpu_ppc_instr.cc
+@@ -2780,7 +2780,7 @@ X(to_be_translated)
+ } else {
+ if (!cpu->translation_readahead)
+ fatal("[ TODO: Unimplemented ALTIVEC, iword"
+- " = 0x%08"PRIx32"x ]\n", iword);
++ " = 0x%08" PRIx32 "x ]\n", iword);
+ goto bad;
+ }
+ break;
+@@ -3918,4 +3918,3 @@ X(to_be_translated)
+ #include "cpu_dyntrans.cc"
+ #undef DYNTRANS_TO_BE_TRANSLATED_TAIL
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__sh.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__sh.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_cpus_cpu__sh.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,189 @@
+$NetBSD: patch-src_cpus_cpu__sh.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/cpus/cpu_sh.cc.orig 2014-08-17 08:45:15.000000000 +0000
++++ src/cpus/cpu_sh.cc
+@@ -462,10 +462,10 @@ void sh_cpu_register_dump(struct cpu *cp
+ symbol = get_symbol_name(&cpu->machine->symbol_context,
+ cpu->pc, &offset);
+
+- debug("cpu%i: pc = 0x%08"PRIx32, x, (uint32_t)cpu->pc);
++ debug("cpu%i: pc = 0x%08" PRIx32, x, (uint32_t)cpu->pc);
+ debug(" <%s>\n", symbol != NULL? symbol : " no symbol ");
+
+- debug("cpu%i: sr = 0x%08"PRIx32" (%s, %s, %s, %s, %s, %s,"
++ debug("cpu%i: sr = 0x%08" PRIx32 " (%s, %s, %s, %s, %s, %s,"
+ " imask=0x%x, %s, %s)\n", x, (int32_t)cpu->cd.sh.sr,
+ (cpu->cd.sh.sr & SH_SR_MD)? "MD" : "!md",
+ (cpu->cd.sh.sr & SH_SR_RB)? "RB" : "!rb",
+@@ -479,11 +479,11 @@ void sh_cpu_register_dump(struct cpu *cp
+
+ symbol = get_symbol_name(&cpu->machine->symbol_context,
+ cpu->cd.sh.pr, &offset);
+- debug("cpu%i: pr = 0x%08"PRIx32, x, (uint32_t)cpu->cd.sh.pr);
++ debug("cpu%i: pr = 0x%08" PRIx32, x, (uint32_t)cpu->cd.sh.pr);
+ debug(" <%s>\n", symbol != NULL? symbol : " no symbol ");
+
+- debug("cpu%i: mach = 0x%08"PRIx32" macl = 0x%08"PRIx32
+- " gbr = 0x%08"PRIx32"\n", x, (uint32_t)cpu->cd.sh.mach,
++ debug("cpu%i: mach = 0x%08" PRIx32" macl = 0x%08" PRIx32
++ " gbr = 0x%08" PRIx32 "\n", x, (uint32_t)cpu->cd.sh.mach,
+ (uint32_t)cpu->cd.sh.macl, (uint32_t)cpu->cd.sh.gbr);
+
+ for (i=0; i<SH_N_GPRS; i++) {
+@@ -497,8 +497,8 @@ void sh_cpu_register_dump(struct cpu *cp
+
+ if (coprocs & 1) {
+ /* Floating point: */
+- debug("cpu%i: fpscr = 0x%08"PRIx32" (%s,%s,%s) fpul = 0x%08"
+- PRIx32"\n", x, cpu->cd.sh.fpscr,
++ debug("cpu%i: fpscr = 0x%08" PRIx32 " (%s,%s,%s) fpul = 0x%08"
++ PRIx32 "\n", x, cpu->cd.sh.fpscr,
+ cpu->cd.sh.fpscr & SH_FPSCR_PR? "PR" : "!pr",
+ cpu->cd.sh.fpscr & SH_FPSCR_SZ? "SZ" : "!sz",
+ cpu->cd.sh.fpscr & SH_FPSCR_FR? "FR" : "!fr",
+@@ -523,13 +523,13 @@ void sh_cpu_register_dump(struct cpu *cp
+
+ if (coprocs & 2) {
+ /* System registers, etc: */
+- debug("cpu%i: vbr = 0x%08"PRIx32" sgr = 0x%08"PRIx32
+- " dbr = 0x%08"PRIx32"\n", x, cpu->cd.sh.vbr, cpu->cd.sh.sgr,
++ debug("cpu%i: vbr = 0x%08" PRIx32 " sgr = 0x%08" PRIx32
++ " dbr = 0x%08" PRIx32 "\n", x, cpu->cd.sh.vbr, cpu->cd.sh.sgr,
+ cpu->cd.sh.dbr);
+- debug("cpu%i: spc = 0x%08"PRIx32" ssr = 0x%08"PRIx32"\n",
++ debug("cpu%i: spc = 0x%08" PRIx32 " ssr = 0x%08" PRIx32 "\n",
+ x, cpu->cd.sh.spc, cpu->cd.sh.ssr);
+- debug("cpu%i: expevt = 0x%"PRIx32" intevt = 0x%"PRIx32
+- " tra = 0x%"PRIx32"\n", x, cpu->cd.sh.expevt,
++ debug("cpu%i: expevt = 0x%" PRIx32 " intevt = 0x%" PRIx32
++ " tra = 0x%" PRIx32 "\n", x, cpu->cd.sh.expevt,
+ cpu->cd.sh.intevt, cpu->cd.sh.tra);
+
+ for (i=0; i<SH_N_GPRS_BANKED; i++) {
+@@ -564,13 +564,13 @@ void sh_cpu_tlbdump(struct machine *m, i
+ continue;
+
+ for (i=0; i<SH_N_ITLB_ENTRIES; i++)
+- printf("cpu%i: itlb_hi_%-2i = 0x%08"PRIx32" "
+- "itlb_lo_%-2i = 0x%08"PRIx32"\n", j, i,
++ printf("cpu%i: itlb_hi_%-2i = 0x%08" PRIx32 " "
++ "itlb_lo_%-2i = 0x%08" PRIx32 "\n", j, i,
+ (uint32_t) cpu->cd.sh.itlb_hi[i], i,
+ (uint32_t) cpu->cd.sh.itlb_lo[i]);
+ for (i=0; i<SH_N_UTLB_ENTRIES; i++)
+- printf("cpu%i: utlb_hi_%-2i = 0x%08"PRIx32" "
+- "utlb_lo_%-2i = 0x%08"PRIx32"\n", j, i,
++ printf("cpu%i: utlb_hi_%-2i = 0x%08" PRIx32 " "
++ "utlb_lo_%-2i = 0x%08" PRIx32 "\n", j, i,
+ (uint32_t) cpu->cd.sh.utlb_hi[i], i,
+ (uint32_t) cpu->cd.sh.utlb_lo[i]);
+ }
+@@ -639,9 +639,9 @@ void sh_exception(struct cpu *cpu, int e
+ else
+ debug("[ exception 0x%03x", expevt);
+
+- debug(", pc=0x%08"PRIx32" ", (uint32_t)cpu->pc);
++ debug(", pc=0x%08" PRIx32 " ", (uint32_t)cpu->pc);
+ if (intevt == 0)
+- debug("vaddr=0x%08"PRIx32" ", vaddr);
++ debug("vaddr=0x%08" PRIx32 " ", vaddr);
+
+ debug(" ]\n");
+ }
+@@ -737,7 +737,7 @@ void sh_exception(struct cpu *cpu, int e
+ * these are not very common.
+ */
+ #if 1
+- printf("\nRESERVED SuperH instruction at spc=%08"PRIx32"\n",
++ printf("\nRESERVED SuperH instruction at spc=%08" PRIx32 "\n",
+ cpu->cd.sh.spc);
+ exit(1);
+ #else
+@@ -790,7 +790,7 @@ int sh_cpu_disassemble_instr(struct cpu
+ if (cpu->machine->ncpus > 1 && running)
+ debug("cpu%i: ", cpu->cpu_id);
+
+- debug("%08"PRIx32, (uint32_t) dumpaddr);
++ debug("%08" PRIx32, (uint32_t) dumpaddr);
+
+ if (cpu->byte_order == EMUL_BIG_ENDIAN)
+ iword = (instr[0] << 8) + instr[1];
+@@ -828,7 +828,7 @@ int sh_cpu_disassemble_instr(struct cpu
+ if (symbol != NULL)
+ debug("<%s>", symbol);
+ else
+- debug("0x%08"PRIx32, addr);
++ debug("0x%08" PRIx32, addr);
+ }
+ debug("\n");
+ } else if (lo4 == 0x7)
+@@ -857,7 +857,7 @@ int sh_cpu_disassemble_instr(struct cpu
+ if (symbol != NULL)
+ debug("<%s>", symbol);
+ else
+- debug("0x%08"PRIx32, addr);
++ debug("0x%08" PRIx32, addr);
+ }
+ debug("\n");
+ } else if (lo8 == 0x12)
+@@ -927,7 +927,7 @@ int sh_cpu_disassemble_instr(struct cpu
+ if (symbol != NULL)
+ debug("<%s>", symbol);
+ else
+- debug("0x%08"PRIx32, addr);
++ debug("0x%08" PRIx32, addr);
+ }
+ debug("\n");
+ break;
+@@ -965,7 +965,7 @@ int sh_cpu_disassemble_instr(struct cpu
+ else
+ debug("UNIMPLEMENTED hi4=0x%x, lo8=0x%02x", hi4, lo8);
+ if (running && lo4 <= 6) {
+- debug("\t; r%i = 0x%08"PRIx32, r8, cpu->cd.sh.r[r8]);
++ debug("\t; r%i = 0x%08" PRIx32, r8, cpu->cd.sh.r[r8]);
+ }
+ debug("\n");
+ break;
+@@ -1133,7 +1133,7 @@ int sh_cpu_disassemble_instr(struct cpu
+ if (symbol != NULL)
+ debug("\t; r%i+%i <%s>", r4, lo4 * 4, symbol);
+ else
+- debug("\t; r%i+%i = 0x%08"PRIx32, r4, lo4 * 4, (int)addr);
++ debug("\t; r%i+%i = 0x%08" PRIx32, r4, lo4 * 4, (int)addr);
+ }
+ debug("\n");
+ break;
+@@ -1173,7 +1173,7 @@ int sh_cpu_disassemble_instr(struct cpu
+ else
+ debug("UNIMPLEMENTED hi4=0x%x, lo8=0x%02x", hi4, lo8);
+ if (running && lo4 < 8 && (lo4 & 3) < 3) {
+- debug("\t; r%i = 0x%08"PRIx32, r4, cpu->cd.sh.r[r4]);
++ debug("\t; r%i = 0x%08" PRIx32, r4, cpu->cd.sh.r[r4]);
+ }
+ debug("\n");
+ break;
+@@ -1187,7 +1187,7 @@ int sh_cpu_disassemble_instr(struct cpu
+ else if (r8 == 0x4)
+ debug("mov.b\t@(%i,r%i),r0", lo4, r4);
+ if (running) {
+- debug("\t; r%i+%i = 0x%08"PRIx32, r4, lo4,
++ debug("\t; r%i+%i = 0x%08" PRIx32, r4, lo4,
+ cpu->cd.sh.r[r4] + lo4);
+ }
+ debug("\n");
+@@ -1197,7 +1197,7 @@ int sh_cpu_disassemble_instr(struct cpu
+ else if (r8 == 0x5)
+ debug("mov.w\t@(%i,r%i),r0", lo4 * 2, r4);
+ if (running) {
+- debug("\t; r%i+%i = 0x%08"PRIx32, r4, lo4 * 2,
++ debug("\t; r%i+%i = 0x%08" PRIx32, r4, lo4 * 2,
+ cpu->cd.sh.r[r4] + lo4 * 2);
+ }
+ debug("\n");
+@@ -1408,4 +1408,3 @@ int sh_cpu_disassemble_instr(struct cpu
+
+
+ #include "tmp_sh_tail.cc"
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_cpus_memory__alpha.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_cpus_memory__alpha.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_cpus_memory__alpha.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,53 @@
+$NetBSD: patch-src_cpus_memory__alpha.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/cpus/memory_alpha.cc.orig 2014-08-17 08:45:15.000000000 +0000
++++ src/cpus/memory_alpha.cc
+@@ -90,7 +90,7 @@ if (vaddr == 0xfffffffd80000000ULL) {
+ return 2;
+ }
+
+- // debug("base = 0x%016"PRIx64"\n", base);
++ // debug("base = 0x%016" PRIx64 "\n", base);
+ if (vaddr == 0xfffffffd80000000ULL) fatal("AYONA3\n");
+
+ uint64_t addr, pte1, pte2, pte3;
+@@ -116,7 +116,7 @@ if (vaddr == 0xfffffffd80000000ULL) fata
+ pte1 = *(uint64_t *)(pt_entry_ptr);
+ pte1 = LE64_TO_HOST(pte1);
+
+- // debug("pte1 = 0x%016"PRIx64"\n", pte1);
++ // debug("pte1 = 0x%016" PRIx64 "\n", pte1);
+ if (!(pte1 & ALPHA_PTE_VALID)) {
+ // TODO:
+ // IF level1_pte<KRE> EQ 0 THEN
+@@ -137,7 +137,7 @@ if (vaddr == 0xfffffffd80000000ULL) fata
+ pte2 = *(uint64_t *)(pt_entry_ptr);
+ pte2 = LE64_TO_HOST(pte2);
+
+- // debug("pte2 = 0x%016"PRIx64"\n", pte2);
++ // debug("pte2 = 0x%016" PRIx64 "\n", pte2);
+ if (!(pte2 & ALPHA_PTE_VALID)) {
+ // TODO:
+ // IF level2_pte<KRE> EQ 0 THEN
+@@ -158,7 +158,7 @@ if (vaddr == 0xfffffffd80000000ULL) fata
+ pte3 = *(uint64_t *)(pt_entry_ptr);
+ pte3 = LE64_TO_HOST(pte3);
+
+- // debug("pte3 = 0x%016"PRIx64"\n", pte3);
++ // debug("pte3 = 0x%016" PRIx64 "\n", pte3);
+
+ if (!(pte3 & ALPHA_PTE_VALID)) {
+ fatal("TODO: pte3 not valid.\n");
+@@ -172,9 +172,8 @@ if (vaddr == 0xfffffffd80000000ULL) fata
+
+ not_found:
+ /* No match. */
+- fatal("[ alpha_translate_v2p: 0x%016"PRIx64" wasn't found ]\n", vaddr);
++ fatal("[ alpha_translate_v2p: 0x%016" PRIx64 " wasn't found ]\n", vaddr);
+ abort();
+ exit(1);
+ return 0;
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_cpus_memory__mips__v2p.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_cpus_memory__mips__v2p.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_cpus_memory__mips__v2p.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,53 @@
+$NetBSD: patch-src_cpus_memory__mips__v2p.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/cpus/memory_mips_v2p.cc.orig 2014-08-17 08:45:15.000000000 +0000
++++ src/cpus/memory_mips_v2p.cc
+@@ -294,7 +294,7 @@ int TRANSLATE_ADDRESS(struct cpu *cpu, u
+ case 0x07fffff: pageshift = 22; break;
+ case 0x1ffffff: pageshift = 24; break;
+ case 0x7ffffff: pageshift = 26; break;
+- default:fatal("pmask=%08"PRIx32"\n", pmask);
++ default:fatal("pmask=%08" PRIx32 "\n", pmask);
+ exit(1);
+ }
+
+@@ -347,8 +347,8 @@ int TRANSLATE_ADDRESS(struct cpu *cpu, u
+ /* Is there a VPN and ASID match? */
+ if (entry_vpn2 == vaddr_vpn2 &&
+ (entry_asid == vaddr_asid || g_bit)) {
+- /* debug("OK MAP 1, i=%i { vaddr=%016"PRIx64" "
+- "==> paddr %016"PRIx64" v=%i d=%i "
++ /* debug("OK MAP 1, i=%i { vaddr=%016" PRIx64 " "
++ "==> paddr %016" PRIx64 " v=%i d=%i "
+ "asid=0x%02x }\n", i, (uint64_t) vaddr,
+ (uint64_t) *return_paddr, v_bit?1:0,
+ d_bit?1:0, vaddr_asid); */
+@@ -357,16 +357,16 @@ int TRANSLATE_ADDRESS(struct cpu *cpu, u
+ writeflag == MEM_READ)) {
+ uint64_t paddr;
+ /* debug("OK MAP 2!!! { w=%i "
+- "vaddr=%016"PRIx64" ==> "
++ "vaddr=%016" PRIx64 " ==> "
+ "d=%i v=%i paddr %016"
+- PRIx64" ",
++ PRIx64 " ",
+ writeflag, (uint64_t)vaddr,
+ d_bit?1:0, v_bit?1:0,
+ (uint64_t) *return_paddr);
+ debug(", tlb entry %2i: ma"
+- "sk=%016"PRIx64" hi=%016"
+- PRIx64" lo0=%016"PRIx64
+- " lo1=%016"PRIx64"\n",
++ "sk=%016" PRIx64 " hi=%016"
++ PRIx64" lo0=%016" PRIx64
++ " lo1=%016" PRIx64 "\n",
+ i, cp0->tlbs[i].mask, cp0->
+ tlbs[i].hi, cp0->tlbs[i].
+ lo0, cp0->tlbs[i].lo1);
+@@ -445,4 +445,3 @@ exception:
+ /* Return failure: */
+ return 0;
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_cpus_memory__ppc.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_cpus_memory__ppc.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_cpus_memory__ppc.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,20 @@
+$NetBSD: patch-src_cpus_memory__ppc.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/cpus/memory_ppc.cc.orig 2014-08-17 08:45:15.000000000 +0000
++++ src/cpus/memory_ppc.cc
+@@ -270,7 +270,7 @@ int ppc_translate_v2p(struct cpu *cpu, u
+ return 0;
+
+ if (!quiet_mode)
+- fatal("[ memory_ppc: exception! vaddr=0x%"PRIx64" pc=0x%"PRIx64
++ fatal("[ memory_ppc: exception! vaddr=0x%" PRIx64 " pc=0x%" PRIx64
+ " instr=%i user=%i wf=%i ]\n", (uint64_t) vaddr,
+ (uint64_t) cpu->pc, instr, user, writeflag);
+
+@@ -295,4 +295,3 @@ int ppc_translate_v2p(struct cpu *cpu, u
+
+ return 0;
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_cpus_memory__sh.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_cpus_memory__sh.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_cpus_memory__sh.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,27 @@
+$NetBSD: patch-src_cpus_memory__sh.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/cpus/memory_sh.cc.orig 2014-08-17 08:45:15.000000000 +0000
++++ src/cpus/memory_sh.cc
+@@ -293,7 +293,7 @@ int sh_translate_v2p(struct cpu *cpu, ui
+ }
+
+ if (flags & FLAG_INSTR) {
+- fatal("TODO: instr at 0x%08"PRIx32"\n", (uint32_t)vaddr);
++ fatal("TODO: instr at 0x%08" PRIx32 "\n", (uint32_t)vaddr);
+ exit(1);
+ }
+
+@@ -312,10 +312,9 @@ int sh_translate_v2p(struct cpu *cpu, ui
+
+ /* The ugly 'if' is just here to fool Compaq CC. */
+ if (!(flags & FLAG_NOEXCEPTIONS)) {
+- fatal("Unimplemented SH vaddr 0x%08"PRIx32"\n", vaddr);
++ fatal("Unimplemented SH vaddr 0x%08" PRIx32 "\n", vaddr);
+ exit(1);
+ }
+
+ return 0;
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_debugger_debugger.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_debugger_debugger.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_debugger_debugger.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,23 @@
+$NetBSD: patch-src_debugger_debugger.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/debugger/debugger.cc.orig 2014-08-17 08:45:14.000000000 +0000
++++ src/debugger/debugger.cc
+@@ -164,9 +164,9 @@ static void show_breakpoint(struct machi
+ {
+ printf("%3i: 0x", i);
+ if (m->cpus[0]->is_32bit)
+- printf("%08"PRIx32, (uint32_t) m->breakpoints.addr[i]);
++ printf("%08" PRIx32, (uint32_t) m->breakpoints.addr[i]);
+ else
+- printf("%016"PRIx64, (uint64_t) m->breakpoints.addr[i]);
++ printf("%016" PRIx64, (uint64_t) m->breakpoints.addr[i]);
+ if (m->breakpoints.string[i] != NULL)
+ printf(" (%s)", m->breakpoints.string[i]);
+ printf("\n");
+@@ -731,4 +731,3 @@ void debugger_init(struct emul *emul)
+ last_cmd_index = 0;
+ repeat_cmd[0] = '\0';
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_debugger_debugger__cmds.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_debugger_debugger__cmds.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_debugger_debugger__cmds.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,141 @@
+$NetBSD: patch-src_debugger_debugger__cmds.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+--- src/debugger/debugger_cmds.cc.orig 2014-08-17 08:45:14.000000000 +0000
++++ src/debugger/debugger_cmds.cc
+@@ -201,7 +201,7 @@ static void debugger_cmd_device(struct m
+ printf("No memory-mapped devices in this machine.\n");
+
+ for (i=0; i<mem->n_mmapped_devices; i++) {
+- printf("%2i: %25s @ 0x%011"PRIx64", len = 0x%"PRIx64,
++ printf("%2i: %25s @ 0x%011" PRIx64 ", len = 0x%" PRIx64,
+ i, mem->devices[i].name,
+ (uint64_t) mem->devices[i].baseaddr,
+ (uint64_t) mem->devices[i].length);
+@@ -313,9 +313,9 @@ static void debugger_cmd_dump(struct mac
+ MEM_READ, CACHE_NONE | NO_EXCEPTIONS);
+
+ if (c->is_32bit)
+- printf("0x%08"PRIx32" ", (uint32_t) addr);
++ printf("0x%08" PRIx32 " ", (uint32_t) addr);
+ else
+- printf("0x%016"PRIx64" ", (uint64_t) addr);
++ printf("0x%016" PRIx64 " ", (uint64_t) addr);
+
+ if (r == MEMORY_ACCESS_FAILED)
+ printf("(memory access failed)\n");
+@@ -491,9 +491,9 @@ static void debugger_cmd_lookup(struct m
+ }
+ printf("%s = 0x", cmd_line);
+ if (m->cpus[0]->is_32bit)
+- printf("%08"PRIx32"\n", (uint32_t) newaddr);
++ printf("%08" PRIx32 "\n", (uint32_t) newaddr);
+ else
+- printf("%016"PRIx64"\n", (uint64_t) newaddr);
++ printf("%016" PRIx64 "\n", (uint64_t) newaddr);
+ return;
+ }
+
+@@ -501,9 +501,9 @@ static void debugger_cmd_lookup(struct m
+
+ if (symbol != NULL) {
+ if (m->cpus[0]->is_32bit)
+- printf("0x%08"PRIx32, (uint32_t) addr);
++ printf("0x%08" PRIx32, (uint32_t) addr);
+ else
+- printf("0x%016"PRIx64, (uint64_t) addr);
++ printf("0x%016" PRIx64, (uint64_t) addr);
+ printf(" = %s\n", symbol);
+ } else
+ printf("lookup for '%s' failed\n", cmd_line);
+@@ -636,16 +636,16 @@ static void debugger_cmd_print(struct ma
+ printf("Multiple matches. Try prefixing with %%, $, or @.\n");
+ break;
+ case PARSE_SETTINGS:
+- printf("%s = 0x%"PRIx64"\n", cmd_line, (uint64_t)tmp);
++ printf("%s = 0x%" PRIx64 "\n", cmd_line, (uint64_t)tmp);
+ break;
+ case PARSE_SYMBOL:
+ if (m->cpus[0]->is_32bit)
+- printf("%s = 0x%08"PRIx32"\n", cmd_line, (uint32_t)tmp);
++ printf("%s = 0x%08" PRIx32 "\n", cmd_line, (uint32_t)tmp);
+ else
+- printf("%s = 0x%016"PRIx64"\n", cmd_line,(uint64_t)tmp);
++ printf("%s = 0x%016" PRIx64 "\n", cmd_line,(uint64_t)tmp);
+ break;
+ case PARSE_NUMBER:
+- printf("0x%"PRIx64"\n", (uint64_t) tmp);
++ printf("0x%" PRIx64 "\n", (uint64_t) tmp);
+ break;
+ }
+ }
+@@ -754,12 +754,12 @@ static void debugger_cmd_put(struct mach
+ case 'b':
+ a_byte = data;
+ if (m->cpus[0]->is_32bit)
+- printf("0x%08"PRIx32, (uint32_t) addr);
++ printf("0x%08" PRIx32, (uint32_t) addr);
+ else
+- printf("0x%016"PRIx64, (uint64_t) addr);
++ printf("0x%016" PRIx64, (uint64_t) addr);
+ printf(": %02x", a_byte);
+ if (data > 255)
+- printf(" (NOTE: truncating %0"PRIx64")",
++ printf(" (NOTE: truncating %0" PRIx64 ")",
+ (uint64_t) data);
+ res = m->cpus[0]->memory_rw(m->cpus[0], m->cpus[0]->mem, addr,
+ &a_byte, 1, MEM_WRITE, CACHE_NONE | NO_EXCEPTIONS);
+@@ -771,12 +771,12 @@ static void debugger_cmd_put(struct mach
+ if ((addr & 1) != 0)
+ printf("WARNING: address isn't aligned\n");
+ if (m->cpus[0]->is_32bit)
+- printf("0x%08"PRIx32, (uint32_t) addr);
++ printf("0x%08" PRIx32, (uint32_t) addr);
+ else
+- printf("0x%016"PRIx64, (uint64_t) addr);
++ printf("0x%016" PRIx64, (uint64_t) addr);
+ printf(": %04x", (int)data);
+ if (data > 0xffff)
+- printf(" (NOTE: truncating %0"PRIx64")",
++ printf(" (NOTE: truncating %0" PRIx64 ")",
+ (uint64_t) data);
+ res = store_16bit_word(m->cpus[0], addr, data);
+ if (!res)
+@@ -787,15 +787,15 @@ static void debugger_cmd_put(struct mach
+ if ((addr & 3) != 0)
+ printf("WARNING: address isn't aligned\n");
+ if (m->cpus[0]->is_32bit)
+- printf("0x%08"PRIx32, (uint32_t) addr);
++ printf("0x%08" PRIx32, (uint32_t) addr);
+ else
+- printf("0x%016"PRIx64, (uint64_t) addr);
++ printf("0x%016" PRIx64, (uint64_t) addr);
+
+ printf(": %08x", (int)data);
+
+ if (data > 0xffffffff && (data >> 32) != 0
+ && (data >> 32) != 0xffffffff)
+- printf(" (NOTE: truncating %0"PRIx64")",
++ printf(" (NOTE: truncating %0" PRIx64 ")",
+ (uint64_t) data);
+
+ res = store_32bit_word(m->cpus[0], addr, data);
+@@ -807,11 +807,11 @@ static void debugger_cmd_put(struct mach
+ if ((addr & 7) != 0)
+ printf("WARNING: address isn't aligned\n");
+ if (m->cpus[0]->is_32bit)
+- printf("0x%08"PRIx32, (uint32_t) addr);
++ printf("0x%08" PRIx32, (uint32_t) addr);
+ else
+- printf("0x%016"PRIx64, (uint64_t) addr);
++ printf("0x%016" PRIx64, (uint64_t) addr);
+
+- printf(": %016"PRIx64, (uint64_t) data);
++ printf(": %016" PRIx64, (uint64_t) data);
+
+ res = store_64bit_word(m->cpus[0], addr, data);
+ if (!res)
+@@ -1381,4 +1381,3 @@ static void debugger_cmd_help(struct mac
+ " registers, '@'\nfor symbols, and '$' for numeric values. Use"
+ " 0x for hexadecimal values.\n");
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_devices_bus__pci.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_devices_bus__pci.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_devices_bus__pci.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,20 @@
+$NetBSD: patch-src_devices_bus__pci.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/devices/bus_pci.cc.orig 2014-08-17 08:45:12.000000000 +0000
++++ src/devices/bus_pci.cc
+@@ -1095,7 +1095,7 @@ printf("reg = 0x%x\n", reg);
+ case PCI_COMMAND_STATUS_REG:
+ if (value & PCI_COMMAND_IO_ENABLE)
+ enabled = 1;
+-printf(" value = 0x%"PRIx32"\n", value);
++printf(" value = 0x%" PRIx32 "\n", value);
+ if (wdc0 != NULL)
+ wdc_set_io_enabled((struct wdc_data *) wdc0, enabled);
+ if (wdc1 != NULL)
+@@ -1429,4 +1429,3 @@ PCIINIT(ati_radeon_9200_2)
+ /* TODO */
+ allocate_device_space(pd, 0x1000, 0x400000, &port, &memaddr);
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__algor.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__algor.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__algor.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,32 @@
+$NetBSD: patch-src_devices_dev__algor.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/devices/dev_algor.cc.orig 2014-08-17 08:45:12.000000000 +0000
++++ src/devices/dev_algor.cc
+@@ -175,17 +175,17 @@ DEVICE_ACCESS(algor)
+ fatal("[ algor: read from 0x%x ]\n",
+ (int)relative_addr);
+ } else {
+- fatal("[ algor: write to 0x%x: 0x%"PRIx64" ]\n",
++ fatal("[ algor: write to 0x%x: 0x%" PRIx64 " ]\n",
+ (int) relative_addr, (uint64_t) idata);
+ }
+ }
+
+ if (n != NULL) {
+ if (writeflag == MEM_READ) {
+- debug("[ algor: read from %s: 0x%"PRIx64" ]\n",
++ debug("[ algor: read from %s: 0x%" PRIx64 " ]\n",
+ n, (uint64_t) odata);
+ } else {
+- debug("[ algor: write to %s: 0x%"PRIx64" ]\n",
++ debug("[ algor: write to %s: 0x%" PRIx64 " ]\n",
+ n, (uint64_t) idata);
+ }
+ }
+@@ -226,4 +226,3 @@ DEVINIT(algor)
+
+ return 1;
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__dreamcast__maple.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__dreamcast__maple.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__dreamcast__maple.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,46 @@
+$NetBSD: patch-src_devices_dev__dreamcast__maple.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/devices/dev_dreamcast_maple.cc.orig 2014-08-17 08:45:12.000000000 +0000
++++ src/devices/dev_dreamcast_maple.cc
+@@ -387,14 +387,14 @@ void maple_do_dma_xfer(struct cpu *cpu,
+ }
+
+ /* debug("[ dreamcast_maple: DMA transfer, dmaaddr = "
+- "0x%08"PRIx32" ]\n", addr); */
++ "0x%08" PRIx32 " ]\n", addr); */
+
+ /*
+ * DMA transfers must be 32-byte aligned, according to Marcus
+ * Comstedt's Maple demo program.
+ */
+ if (addr & 0x1f) {
+- fatal("[ dreamcast_maple: dmaaddr 0x%08"PRIx32" is NOT"
++ fatal("[ dreamcast_maple: dmaaddr 0x%08" PRIx32 " is NOT"
+ " 32-byte aligned; aborting ]\n", addr);
+ return;
+ }
+@@ -432,7 +432,7 @@ void maple_do_dma_xfer(struct cpu *cpu,
+
+ if (receive_addr & 0xe000001f)
+ fatal("[ dreamcast_maple: WARNING! receive address 0x"
+- "%08"PRIx32" isn't valid! ]\n", receive_addr);
++ "%08" PRIx32 " isn't valid! ]\n", receive_addr);
+
+ /* Read the command word for this message: */
+ cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *) (void *) &buf, 4, MEM_READ,
+@@ -515,7 +515,7 @@ void maple_do_dma_xfer(struct cpu *cpu,
+ d, cpu, port, receive_addr);
+ } else {
+ fatal("[ dreamcast_maple: WARNING: GETCOND: "
+- "UNIMPLEMENTED 0x%08"PRIx32" ]\n", cond);
++ "UNIMPLEMENTED 0x%08" PRIx32 " ]\n", cond);
+ exit(1);
+ }
+ break;
+@@ -665,4 +665,3 @@ DEVINIT(dreamcast_maple)
+
+ return 1;
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__lca.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__lca.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__lca.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,56 @@
+$NetBSD: patch-src_devices_dev__lca.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/devices/dev_lca.cc.orig 2014-08-17 08:45:12.000000000 +0000
++++ src/devices/dev_lca.cc
+@@ -221,7 +221,7 @@ DEVICE_ACCESS(lca_ioc)
+ /* TODO: Actually implement this. */
+ if (idata & ~IOC_TB_ENA_TEN) {
+ fatal("TODO: LCA_IOC_TB_ENA value "
+- " (0x%"PRIx64") has unimplemented "
++ " (0x%" PRIx64 ") has unimplemented "
+ "bits.\n", (uint64_t)idata);
+ exit(1);
+ }
+@@ -236,7 +236,7 @@ DEVICE_ACCESS(lca_ioc)
+ /* TODO: Actually implement this. */
+ if (idata != 0ULL && idata != 0x300800000ULL) {
+ fatal("TODO: LCA_IOC_W_BASE0 value differs"
+- " (0x%"PRIx64") from the only implemented"
++ " (0x%" PRIx64 ") from the only implemented"
+ " values\n", (uint64_t)idata);
+ exit(1);
+ }
+@@ -251,7 +251,7 @@ DEVICE_ACCESS(lca_ioc)
+ /* TODO: Actually implement this. */
+ if (idata != 0x700000ULL) {
+ fatal("TODO: LCA_IOC_W_MASK0 value differs"
+- " (0x%"PRIx64") from the only implemented"
++ " (0x%" PRIx64 ") from the only implemented"
+ " value\n", (uint64_t)idata);
+ exit(1);
+ }
+@@ -275,7 +275,7 @@ DEVICE_ACCESS(lca_ioc)
+ /* TODO: Actually implement this. */
+ if (idata != 0x240000000ULL) {
+ fatal("TODO: LCA_IOC_W_BASE1 value differs"
+- " (0x%"PRIx64") from the only implemented"
++ " (0x%" PRIx64 ") from the only implemented"
+ " value\n", (uint64_t)idata);
+ exit(1);
+ }
+@@ -290,7 +290,7 @@ DEVICE_ACCESS(lca_ioc)
+ /* TODO: Actually implement this. */
+ if (idata != 0x3ff00000ULL) {
+ fatal("TODO: LCA_IOC_W_MASK1 value differs"
+- " (0x%"PRIx64") from the only implemented"
++ " (0x%" PRIx64 ") from the only implemented"
+ " value\n", (uint64_t)idata);
+ exit(1);
+ }
+@@ -378,4 +378,3 @@ DEVINIT(lca)
+
+ return 1;
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__pvr.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__pvr.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__pvr.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,199 @@
+$NetBSD: patch-src_devices_dev__pvr.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/devices/dev_pvr.cc.orig 2014-08-17 08:45:12.000000000 +0000
++++ src/devices/dev_pvr.cc
+@@ -1595,11 +1595,11 @@ DEVICE_ACCESS(pvr)
+
+ case PVRREG_OB_ADDR:
+ if (writeflag == MEM_WRITE) {
+- debug("[ pvr: OB_ADDR set to 0x%08"PRIx32" ]\n",
++ debug("[ pvr: OB_ADDR set to 0x%08" PRIx32 " ]\n",
+ (uint32_t)(idata & PVR_OB_ADDR_MASK));
+ if (idata & ~PVR_OB_ADDR_MASK) {
+ fatal("[ pvr: OB_ADDR: Fatal error: Unknown"
+- " bits set: 0x%08"PRIx32" ]\n",
++ " bits set: 0x%08" PRIx32 " ]\n",
+ (uint32_t)(idata & ~PVR_OB_ADDR_MASK));
+ exit(1);
+ }
+@@ -1610,11 +1610,11 @@ DEVICE_ACCESS(pvr)
+
+ case PVRREG_TILEBUF_ADDR:
+ if (writeflag == MEM_WRITE) {
+- debug("[ pvr: TILEBUF_ADDR set to 0x%08"PRIx32" ]\n",
++ debug("[ pvr: TILEBUF_ADDR set to 0x%08" PRIx32 " ]\n",
+ (uint32_t)(idata & PVR_TILEBUF_ADDR_MASK));
+ if (idata & ~PVR_TILEBUF_ADDR_MASK) {
+ fatal("[ pvr: TILEBUF_ADDR: Unknown"
+- " bits set: 0x%08"PRIx32" ]\n",
++ " bits set: 0x%08" PRIx32 " ]\n",
+ (uint32_t)(idata & ~PVR_TILEBUF_ADDR_MASK));
+ exit(1);
+ }
+@@ -1640,7 +1640,7 @@ DEVICE_ACCESS(pvr)
+
+ case PVRREG_BRDCOLR:
+ if (writeflag == MEM_WRITE) {
+- debug("[ pvr: BRDCOLR set to 0x%06"PRIx32" ]\n",
++ debug("[ pvr: BRDCOLR set to 0x%06" PRIx32 " ]\n",
+ (int)idata);
+ DEFAULT_WRITE;
+ d->border_updated = 1;
+@@ -1701,7 +1701,7 @@ DEVICE_ACCESS(pvr)
+
+ case PVRREG_FB_RENDER_ADDR1:
+ if (writeflag == MEM_WRITE) {
+- debug("[ pvr: FB_RENDER_ADDR1 set to 0x%08"PRIx32
++ debug("[ pvr: FB_RENDER_ADDR1 set to 0x%08" PRIx32
+ " ]\n", (int) idata);
+ DEFAULT_WRITE;
+ }
+@@ -1709,7 +1709,7 @@ DEVICE_ACCESS(pvr)
+
+ case PVRREG_FB_RENDER_ADDR2:
+ if (writeflag == MEM_WRITE) {
+- debug("[ pvr: FB_RENDER_ADDR2 set to 0x%08"PRIx32
++ debug("[ pvr: FB_RENDER_ADDR2 set to 0x%08" PRIx32
+ " ]\n", (int) idata);
+ DEFAULT_WRITE;
+ }
+@@ -1802,10 +1802,10 @@ DEVICE_ACCESS(pvr)
+
+ case PVRREG_VRAM_CFG1:
+ if (writeflag == MEM_WRITE) {
+- debug("[ pvr: VRAM_CFG1 set to 0x%08"PRIx32,
++ debug("[ pvr: VRAM_CFG1 set to 0x%08" PRIx32,
+ (int) idata);
+ if (idata != VRAM_CFG1_GOOD_REFRESH_VALUE)
+- fatal("{ VRAM_CFG1 = 0x%08"PRIx32" is not "
++ fatal("{ VRAM_CFG1 = 0x%08" PRIx32 " is not "
+ "yet implemented! }", (int) idata);
+ debug(" ]\n");
+ DEFAULT_WRITE;
+@@ -1814,10 +1814,10 @@ DEVICE_ACCESS(pvr)
+
+ case PVRREG_VRAM_CFG2:
+ if (writeflag == MEM_WRITE) {
+- debug("[ pvr: VRAM_CFG2 set to 0x%08"PRIx32,
++ debug("[ pvr: VRAM_CFG2 set to 0x%08" PRIx32,
+ (int) idata);
+ if (idata != VRAM_CFG2_UNKNOWN_MAGIC)
+- fatal("{ VRAM_CFG2 = 0x%08"PRIx32" is not "
++ fatal("{ VRAM_CFG2 = 0x%08" PRIx32 " is not "
+ "yet implemented! }", (int) idata);
+ debug(" ]\n");
+ DEFAULT_WRITE;
+@@ -1826,10 +1826,10 @@ DEVICE_ACCESS(pvr)
+
+ case PVRREG_VRAM_CFG3:
+ if (writeflag == MEM_WRITE) {
+- debug("[ pvr: VRAM_CFG3 set to 0x%08"PRIx32,
++ debug("[ pvr: VRAM_CFG3 set to 0x%08" PRIx32,
+ (int) idata);
+ if (idata != VRAM_CFG3_UNKNOWN_MAGIC)
+- fatal("{ VRAM_CFG3 = 0x%08"PRIx32" is not "
++ fatal("{ VRAM_CFG3 = 0x%08" PRIx32 " is not "
+ "yet implemented! }", (int) idata);
+ debug(" ]\n");
+ DEFAULT_WRITE;
+@@ -1838,7 +1838,7 @@ DEVICE_ACCESS(pvr)
+
+ case PVRREG_FOG_TABLE_COL:
+ if (writeflag == MEM_WRITE) {
+- debug("[ pvr: FOG_TABLE_COL set to 0x%06"PRIx32" ]\n",
++ debug("[ pvr: FOG_TABLE_COL set to 0x%06" PRIx32 " ]\n",
+ (int) idata);
+ DEFAULT_WRITE;
+ }
+@@ -1846,7 +1846,7 @@ DEVICE_ACCESS(pvr)
+
+ case PVRREG_FOG_VERTEX_COL:
+ if (writeflag == MEM_WRITE) {
+- debug("[ pvr: FOG_VERTEX_COL set to 0x%06"PRIx32" ]\n",
++ debug("[ pvr: FOG_VERTEX_COL set to 0x%06" PRIx32 " ]\n",
+ (int) idata);
+ DEFAULT_WRITE;
+ }
+@@ -1854,7 +1854,7 @@ DEVICE_ACCESS(pvr)
+
+ case PVRREG_FOG_DENSITY:
+ if (writeflag == MEM_WRITE) {
+- debug("[ pvr: FOG_DENSITY set to 0x%08"PRIx32" ]\n",
++ debug("[ pvr: FOG_DENSITY set to 0x%08" PRIx32 " ]\n",
+ (int) idata);
+ DEFAULT_WRITE;
+ }
+@@ -1862,7 +1862,7 @@ DEVICE_ACCESS(pvr)
+
+ case PVRREG_CLAMP_MAX:
+ if (writeflag == MEM_WRITE) {
+- debug("[ pvr: CLAMP_MAX set to 0x%06"PRIx32" ]\n",
++ debug("[ pvr: CLAMP_MAX set to 0x%06" PRIx32 " ]\n",
+ (int) idata);
+ DEFAULT_WRITE;
+ }
+@@ -1870,7 +1870,7 @@ DEVICE_ACCESS(pvr)
+
+ case PVRREG_CLAMP_MIN:
+ if (writeflag == MEM_WRITE) {
+- debug("[ pvr: CLAMP_MIN set to 0x%06"PRIx32" ]\n",
++ debug("[ pvr: CLAMP_MIN set to 0x%06" PRIx32 " ]\n",
+ (int) idata);
+ DEFAULT_WRITE;
+ }
+@@ -1896,7 +1896,7 @@ DEVICE_ACCESS(pvr)
+
+ case PVRREG_DIWADDRL:
+ if (writeflag == MEM_WRITE) {
+- debug("[ pvr: DIWADDRL set to 0x%08"PRIx32" ]\n",
++ debug("[ pvr: DIWADDRL set to 0x%08" PRIx32 " ]\n",
+ (int) idata);
+ pvr_fb_invalidate(d, -1, -1);
+ DEFAULT_WRITE;
+@@ -1905,7 +1905,7 @@ DEVICE_ACCESS(pvr)
+
+ case PVRREG_DIWADDRS:
+ if (writeflag == MEM_WRITE) {
+- debug("[ pvr: DIWADDRS set to 0x%08"PRIx32" ]\n",
++ debug("[ pvr: DIWADDRS set to 0x%08" PRIx32 " ]\n",
+ (int) idata);
+ pvr_fb_invalidate(d, -1, -1);
+ DEFAULT_WRITE;
+@@ -2056,10 +2056,10 @@ DEVICE_ACCESS(pvr)
+
+ case PVRREG_MAGIC_110:
+ if (writeflag == MEM_WRITE) {
+- debug("[ pvr: MAGIC_110 set to 0x%08"PRIx32,
++ debug("[ pvr: MAGIC_110 set to 0x%08" PRIx32,
+ (int) idata);
+ if (idata != MAGIC_110_VALUE)
+- fatal("{ MAGIC_110 = 0x%08"PRIx32" is not "
++ fatal("{ MAGIC_110 = 0x%08" PRIx32 " is not "
+ "yet implemented! }", (int) idata);
+ debug(" ]\n");
+ DEFAULT_WRITE;
+@@ -2068,7 +2068,7 @@ DEVICE_ACCESS(pvr)
+
+ case PVRREG_TA_LUMINANCE:
+ if (writeflag == MEM_WRITE) {
+- debug("[ pvr: TA_LUMINANCE set to 0x%08"PRIx32" ]\n",
++ debug("[ pvr: TA_LUMINANCE set to 0x%08" PRIx32 " ]\n",
+ (int) idata);
+ DEFAULT_WRITE;
+ }
+@@ -2175,7 +2175,7 @@ DEVICE_ACCESS(pvr)
+ pvr_ta_init(cpu, d);
+
+ if (idata != PVR_TA_INIT && idata != 0)
+- fatal("{ TA_INIT = 0x%08"PRIx32" is not "
++ fatal("{ TA_INIT = 0x%08" PRIx32 " is not "
+ "yet implemented! }", (int) idata);
+
+ /* Always reset to 0. */
+@@ -2558,4 +2558,3 @@ DEVINIT(pvr)
+
+ return 1;
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__sgi__mardigras.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__sgi__mardigras.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__sgi__mardigras.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,29 @@
+$NetBSD: patch-src_devices_dev__sgi__mardigras.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/devices/dev_sgi_mardigras.cc.orig 2014-08-17 08:45:12.000000000 +0000
++++ src/devices/dev_sgi_mardigras.cc
+@@ -203,7 +203,7 @@ void mardigras_20400(struct cpu *cpu, st
+ return;
+ }
+
+- debug("mardigras_20400(): 0x%016"PRIx64"\n", (uint64_t) idata);
++ debug("mardigras_20400(): 0x%016" PRIx64 "\n", (uint64_t) idata);
+ }
+
+
+@@ -285,7 +285,7 @@ DEVICE_ACCESS(sgi_mardigras)
+ debug("[ sgi_mardigras: read from 0x%08lx ]\n",
+ (long)relative_addr);
+ } else {
+- debug("[ sgi_mardigras: write to 0x%08lx: 0x%016"PRIx64
++ debug("[ sgi_mardigras: write to 0x%08lx: 0x%016" PRIx64
+ " ]\n", (long) relative_addr, (uint64_t) idata);
+ }
+ }
+@@ -319,4 +319,3 @@ DEVINIT(sgi_mardigras)
+
+ return 1;
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__vga.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__vga.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__vga.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,22 @@
+$NetBSD: patch-src_devices_dev__vga.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/devices/dev_vga.cc.orig 2014-08-17 08:45:12.000000000 +0000
++++ src/devices/dev_vga.cc
+@@ -516,8 +516,8 @@ DEVICE_TICK(vga)
+ int base = ((d->crtc_reg[VGA_CRTC_START_ADDR_HIGH] << 8)
+ + d->crtc_reg[VGA_CRTC_START_ADDR_LOW]) * 2;
+ int new_u_y1, new_u_y2;
+- debug("[ dev_vga_tick: dyntrans access, %"PRIx64" .. %"
+- PRIx64" ]\n", (uint64_t) low, (uint64_t) high);
++ debug("[ dev_vga_tick: dyntrans access, %" PRIx64 " .. %"
++ PRIx64 " ]\n", (uint64_t) low, (uint64_t) high);
+ low -= base;
+ high -= base;
+ d->update_x1 = 0;
+@@ -1266,4 +1266,3 @@ void dev_vga_init(struct machine *machin
+
+ vga_update_cursor(machine, d);
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__vr41xx.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__vr41xx.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__vr41xx.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,43 @@
+$NetBSD: patch-src_devices_dev__vr41xx.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/devices/dev_vr41xx.cc.orig 2014-08-17 08:45:12.000000000 +0000
++++ src/devices/dev_vr41xx.cc
+@@ -466,7 +466,7 @@ static uint64_t vr41xx_kiu(struct cpu *c
+ default:
+ if (writeflag == MEM_WRITE)
+ debug("[ vr41xx KIU: unimplemented write to offset "
+- "0x%x, data=0x%016"PRIx64" ]\n", ofs,
++ "0x%x, data=0x%016" PRIx64 " ]\n", ofs,
+ (uint64_t) idata);
+ else
+ debug("[ vr41xx KIU: unimplemented read from offset "
+@@ -638,11 +638,11 @@ DEVICE_ACCESS(vr41xx)
+ default:
+ if (writeflag == MEM_WRITE)
+ debug("[ vr41xx: unimplemented write to address "
+- "0x%"PRIx64", data=0x%016"PRIx64" ]\n",
++ "0x%" PRIx64 ", data=0x%016" PRIx64 " ]\n",
+ (uint64_t) relative_addr, (uint64_t) idata);
+ else
+ debug("[ vr41xx: unimplemented read from address "
+- "0x%"PRIx64" ]\n", (uint64_t) relative_addr);
++ "0x%" PRIx64 " ]\n", (uint64_t) relative_addr);
+ }
+
+ ret:
+@@ -776,7 +776,7 @@ struct vr41xx_data *dev_vr41xx_init(stru
+ */
+ if (cpumodel == 4131) {
+ snprintf(tmps, sizeof(tmps), "ns16550 irq=%s.cpu[%i].vrip.%i "
+- "addr=0x%"PRIx64" name2=siu", machine->path,
++ "addr=0x%" PRIx64 " name2=siu", machine->path,
+ machine->bootstrap_cpu, VRIP_INTR_SIU,
+ (uint64_t) (baseaddr+0x800));
+ device_add(machine, tmps);
+@@ -804,4 +804,3 @@ struct vr41xx_data *dev_vr41xx_init(stru
+
+ return d;
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__wdc.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__wdc.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__wdc.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,47 @@
+$NetBSD: patch-src_devices_dev__wdc.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/devices/dev_wdc.cc.orig 2014-08-17 08:45:12.000000000 +0000
++++ src/devices/dev_wdc.cc
+@@ -580,13 +580,13 @@ DEVICE_ACCESS(wdc)
+ }
+
+ if (d->data_debug) {
+- const char *s = "0x%04"PRIx64" ]\n";
++ const char *s = "0x%04" PRIx64 " ]\n";
+ if (len == 1)
+- s = "0x%02"PRIx64" ]\n";
++ s = "0x%02" PRIx64 " ]\n";
+ if (len == 4)
+- s = "0x%08"PRIx64" ]\n";
++ s = "0x%08" PRIx64 " ]\n";
+ if (len == 8)
+- s = "0x%016"PRIx64" ]\n";
++ s = "0x%016" PRIx64 " ]\n";
+ debug("[ wdc: read from DATA: ");
+ debug(s, (uint64_t) odata);
+ }
+@@ -621,13 +621,13 @@ DEVICE_ACCESS(wdc)
+ } else {
+ int inbuf_len;
+ if (d->data_debug) {
+- const char *s = "0x%04"PRIx64" ]\n";
++ const char *s = "0x%04" PRIx64 " ]\n";
+ if (len == 1)
+- s = "0x%02"PRIx64" ]\n";
++ s = "0x%02" PRIx64 " ]\n";
+ if (len == 4)
+- s = "0x%08"PRIx64" ]\n";
++ s = "0x%08" PRIx64 " ]\n";
+ if (len == 8)
+- s = "0x%016"PRIx64" ]\n";
++ s = "0x%016" PRIx64 " ]\n";
+ debug("[ wdc: write to DATA: ");
+ debug(s, (uint64_t) idata);
+ }
+@@ -960,4 +960,3 @@ DEVINIT(wdc)
+
+ return 1;
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_disk_bootblock.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_disk_bootblock.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_disk_bootblock.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,30 @@
+$NetBSD: patch-src_disk_bootblock.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/disk/bootblock.cc.orig 2014-08-17 08:45:14.000000000 +0000
++++ src/disk/bootblock.cc
+@@ -177,7 +177,7 @@ int load_bootblock(struct machine *m, st
+ /* Convert loadaddr to uncached: */
+ if ((bootblock_loadaddr & 0xf0000000ULL) != 0x80000000 &&
+ (bootblock_loadaddr & 0xf0000000ULL) != 0xa0000000) {
+- fatal("\nWARNING! Weird load address 0x%08"PRIx32
++ fatal("\nWARNING! Weird load address 0x%08" PRIx32
+ " for SCSI id %i.\n\n",
+ (uint32_t)bootblock_loadaddr, boot_disk_id);
+ if (bootblock_loadaddr == 0) {
+@@ -198,7 +198,7 @@ int load_bootblock(struct machine *m, st
+ bootblock_pc |= 0xffffffffa0000000ULL;
+ cpu->pc = bootblock_pc;
+
+- debug("DEC boot: loadaddr=0x%08"PRIx32", pc=0x%08"PRIx32,
++ debug("DEC boot: loadaddr=0x%08" PRIx32 ", pc=0x%08" PRIx32,
+ (uint32_t) bootblock_loadaddr, (uint32_t) bootblock_pc);
+
+ readofs = 0x18;
+@@ -311,5 +311,3 @@ ret_ok:
+ free(bootblock_buf);
+ return retval;
+ }
+-
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_disk_diskimage.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_disk_diskimage.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_disk_diskimage.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,20 @@
+$NetBSD: patch-src_disk_diskimage.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/disk/diskimage.cc.orig 2014-08-17 08:45:14.000000000 +0000
++++ src/disk/diskimage.cc
+@@ -732,7 +732,7 @@ int diskimage_add(struct machine *machin
+ if (*fname == ':' || *fname == ';')
+ fname ++;
+ if (override_base_offset < 0) {
+- fatal("Bad base offset: %"PRIi64
++ fatal("Bad base offset: %" PRIi64
+ "\n", override_base_offset);
+ exit(1);
+ }
+@@ -1132,4 +1132,3 @@ void diskimage_dump_info(struct machine
+ d = d->next;
+ }
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_file_file__elf.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_file_file__elf.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_file_file__elf.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,117 @@
+$NetBSD: patch-src_file_file__elf.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/file/file_elf.cc.orig 2014-08-17 08:45:10.000000000 +0000
++++ src/file/file_elf.cc
+@@ -326,9 +326,9 @@ static void file_load_elf(struct machine
+ encoding == ELFDATA2LSB? "LSB (LE)" : "MSB (BE)", s);
+
+ if (elf64)
+- debug("%016"PRIx64"\n", (uint64_t) eentry);
++ debug("%016" PRIx64 "\n", (uint64_t) eentry);
+ else
+- debug("%08"PRIx32"\n", (uint32_t) eentry);
++ debug("%08" PRIx32 "\n", (uint32_t) eentry);
+
+ /*
+ * SH64: 32-bit instruction encoding?
+@@ -400,34 +400,34 @@ static void file_load_elf(struct machine
+ if (p_type == PT_LOAD)
+ debug("load");
+ else
+- debug("0x%08"PRIx32, (uint32_t) p_type);
++ debug("0x%08" PRIx32, (uint32_t) p_type);
+
+- debug(") @ 0x%"PRIx64", vaddr 0x", (uint64_t) p_offset);
++ debug(") @ 0x%" PRIx64 ", vaddr 0x", (uint64_t) p_offset);
+
+ if (elf64)
+- debug("%016"PRIx64, (uint64_t) p_vaddr);
++ debug("%016" PRIx64, (uint64_t) p_vaddr);
+ else
+- debug("%08"PRIx32, (uint32_t) p_vaddr);
++ debug("%08" PRIx32, (uint32_t) p_vaddr);
+
+- debug(" len=0x%"PRIx64"\n", (uint64_t) p_memsz);
++ debug(" len=0x%" PRIx64 "\n", (uint64_t) p_memsz);
+
+ if (p_vaddr != p_paddr) {
+ if (elf64)
+- debug("NOTE: vaddr (0x%"PRIx64") and "
+- "paddr (0x%"PRIx64") differ; using "
++ debug("NOTE: vaddr (0x%" PRIx64 ") and "
++ "paddr (0x%" PRIx64 ") differ; using "
+ "vaddr\n", (uint64_t) p_vaddr,
+ (uint64_t) p_paddr);
+ else
+- debug("NOTE: vaddr (0x%08"PRIx32") and "
+- "paddr (0x%08"PRIx32") differ; usin"
++ debug("NOTE: vaddr (0x%08" PRIx32 ") and "
++ "paddr (0x%08" PRIx32 ") differ; usin"
+ "g vaddr\n", (uint32_t) p_vaddr,
+ (uint32_t)p_paddr);
+ }
+
+ if (p_memsz < p_filesz) {
+ fprintf(stderr, "%s: memsz < filesz. TODO: how"
+- " to handle this? memsz=%016"PRIx64
+- " filesz=%016"PRIx64"\n", filename,
++ " to handle this? memsz=%016" PRIx64
++ " filesz=%016" PRIx64 "\n", filename,
+ (uint64_t) p_memsz, (uint64_t) p_filesz);
+ exit(1);
+ }
+@@ -493,7 +493,7 @@ static void file_load_elf(struct machine
+ off_t sh_offset;
+ int n_entries; /* for reading the symbol / string tables */
+
+- /* debug("section header %i at %016"PRIx64"\n", i,
++ /* debug("section header %i at %016" PRIx64 "\n", i,
+ (uint64_t) eshoff+i*eshentsize); */
+
+ fseek(f, eshoff + i * eshentsize, SEEK_SET);
+@@ -576,7 +576,7 @@ static void file_load_elf(struct machine
+ exit(1);
+ }
+
+- debug("%i symbol entries at 0x%"PRIx64"\n",
++ debug("%i symbol entries at 0x%" PRIx64 "\n",
+ (int) n_entries, (uint64_t) sh_offset);
+
+ n_symbols = n_entries;
+@@ -604,7 +604,7 @@ static void file_load_elf(struct machine
+ exit(1);
+ }
+
+- debug("%i bytes of symbol strings at 0x%"PRIx64"\n",
++ debug("%i bytes of symbol strings at 0x%" PRIx64 "\n",
+ (int) sh_size, (uint64_t) sh_offset);
+
+ symbol_strings[sh_size] = '\0';
+@@ -654,9 +654,9 @@ static void file_load_elf(struct machine
+ if (strcmp(symbol_strings + st_name, "_gp") == 0) {
+ debug("found _gp address: 0x");
+ if (elf64)
+- debug("%016"PRIx64"\n", (uint64_t)addr);
++ debug("%016" PRIx64 "\n", (uint64_t)addr);
+ else
+- debug("%08"PRIx32"\n", (uint32_t)addr);
++ debug("%08" PRIx32 "\n", (uint32_t)addr);
+ *gpp = addr;
+ }
+ }
+@@ -709,7 +709,7 @@ static void file_load_elf(struct machine
+ ((uint64_t)b[5] << 16) + ((uint64_t)b[6] << 8) +
+ (uint64_t)b[7];
+
+- debug("entrypoint 0x%016"PRIx64", toc_base 0x%016"PRIx64"\n",
++ debug("entrypoint 0x%016" PRIx64 ", toc_base 0x%016" PRIx64 "\n",
+ (uint64_t) *entrypointp, (uint64_t) toc_base);
+ if (tocp != NULL)
+ *tocp = toc_base;
+@@ -717,4 +717,3 @@ static void file_load_elf(struct machine
+
+ n_executables_loaded ++;
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_file_file__raw.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_file_file__raw.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_file_file__raw.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,25 @@
+$NetBSD: patch-src_file_file__raw.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/file/file_raw.cc.orig 2014-08-17 08:45:10.000000000 +0000
++++ src/file/file_raw.cc
+@@ -111,11 +111,11 @@ static void file_load_raw(struct machine
+ vaddr += len;
+ }
+
+- debug("RAW: 0x%"PRIx64" bytes @ 0x%08"PRIx64,
++ debug("RAW: 0x%" PRIx64 " bytes @ 0x%08" PRIx64,
+ (uint64_t) (ftello(f) - skip), (uint64_t) loadaddr);
+
+ if (skip != 0)
+- debug(" (0x%"PRIx64" bytes of header skipped)",
++ debug(" (0x%" PRIx64 " bytes of header skipped)",
+ (uint64_t) skip);
+
+ debug("\n");
+@@ -126,4 +126,3 @@ static void file_load_raw(struct machine
+
+ n_executables_loaded ++;
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_machines_machine__landisk.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_machines_machine__landisk.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_machines_machine__landisk.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,20 @@
+$NetBSD: patch-src_machines_machine__landisk.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/machines/machine_landisk.cc.orig 2014-08-17 08:45:14.000000000 +0000
++++ src/machines/machine_landisk.cc
+@@ -90,7 +90,7 @@ MACHINE_SETUP(landisk)
+ device_add(machine, tmpstr);
+
+ /* rsclock0 at shb0: RS5C313 real time clock */
+- snprintf(tmpstr, sizeof(tmpstr), "rs5c313 addr=0x%"PRIx64,
++ snprintf(tmpstr, sizeof(tmpstr), "rs5c313 addr=0x%" PRIx64,
+ (uint64_t) SCI_DEVICE_BASE);
+ device_add(machine, tmpstr);
+
+@@ -142,4 +142,3 @@ MACHINE_REGISTER(landisk)
+ machine_entry_add_alias(me, "landisk");
+ machine_entry_add_alias(me, "usl-5p");
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_machines_machine__test.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_machines_machine__test.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_machines_machine__test.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,94 @@
+$NetBSD: patch-src_machines_machine__test.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/machines/machine_test.cc.orig 2014-08-17 08:45:14.000000000 +0000
++++ src/machines/machine_test.cc
+@@ -106,37 +106,37 @@ static void default_test(struct machine
+ snprintf(base_irq, sizeof(base_irq), "%s.cpu[%i]%s",
+ machine->path, machine->bootstrap_cpu, end_of_base_irq);
+
+- snprintf(tmpstr, sizeof(tmpstr), "irqc addr=0x%"PRIx64" irq=%s",
++ snprintf(tmpstr, sizeof(tmpstr), "irqc addr=0x%" PRIx64 " irq=%s",
+ (uint64_t) DEV_IRQC_ADDRESS, base_irq);
+ device_add(machine, tmpstr);
+
+
+ /* Now, add the other devices: */
+
+- snprintf(tmpstr, sizeof(tmpstr), "cons addr=0x%"PRIx64
++ snprintf(tmpstr, sizeof(tmpstr), "cons addr=0x%" PRIx64
+ " irq=%s.irqc.2 in_use=%i",
+ (uint64_t) DEV_CONS_ADDRESS, base_irq, machine->arch != ARCH_SH);
+ machine->main_console_handle = (size_t)device_add(machine, tmpstr);
+
+- snprintf(tmpstr, sizeof(tmpstr), "mp addr=0x%"PRIx64" irq=%s%sirqc.6",
++ snprintf(tmpstr, sizeof(tmpstr), "mp addr=0x%" PRIx64 " irq=%s%sirqc.6",
+ (uint64_t) DEV_MP_ADDRESS,
+ end_of_base_irq[0]? end_of_base_irq + 1 : "",
+ end_of_base_irq[0]? "." : "");
+ device_add(machine, tmpstr);
+
+- snprintf(tmpstr, sizeof(tmpstr), "fbctrl addr=0x%"PRIx64,
++ snprintf(tmpstr, sizeof(tmpstr), "fbctrl addr=0x%" PRIx64,
+ (uint64_t) DEV_FBCTRL_ADDRESS);
+ device_add(machine, tmpstr);
+
+- snprintf(tmpstr, sizeof(tmpstr), "disk addr=0x%"PRIx64,
++ snprintf(tmpstr, sizeof(tmpstr), "disk addr=0x%" PRIx64,
+ (uint64_t) DEV_DISK_ADDRESS);
+ device_add(machine, tmpstr);
+
+- snprintf(tmpstr, sizeof(tmpstr), "ether addr=0x%"PRIx64" irq=%s.irqc.3",
++ snprintf(tmpstr, sizeof(tmpstr), "ether addr=0x%" PRIx64 " irq=%s.irqc.3",
+ (uint64_t) DEV_ETHER_ADDRESS, base_irq);
+ device_add(machine, tmpstr);
+
+- snprintf(tmpstr, sizeof(tmpstr), "rtc addr=0x%"PRIx64" irq=%s.irqc.4",
++ snprintf(tmpstr, sizeof(tmpstr), "rtc addr=0x%" PRIx64 " irq=%s.irqc.4",
+ (uint64_t) DEV_RTC_ADDRESS, base_irq);
+ device_add(machine, tmpstr);
+ }
+@@ -279,29 +279,29 @@ MACHINE_SETUP(oldtestmips)
+ machine->machine_name = strdup("MIPS test machine");
+ cpu->byte_order = EMUL_BIG_ENDIAN;
+
+- snprintf(tmpstr, sizeof(tmpstr), "cons addr=0x%"PRIx64" irq=%s."
++ snprintf(tmpstr, sizeof(tmpstr), "cons addr=0x%" PRIx64 " irq=%s."
+ "cpu[%i].2", (uint64_t) DEV_CONS_ADDRESS, machine->path,
+ machine->bootstrap_cpu);
+ machine->main_console_handle = (size_t)device_add(machine, tmpstr);
+
+- snprintf(tmpstr, sizeof(tmpstr), "mp addr=0x%"PRIx64" irq=6",
++ snprintf(tmpstr, sizeof(tmpstr), "mp addr=0x%" PRIx64 " irq=6",
+ (uint64_t) DEV_MP_ADDRESS);
+ device_add(machine, tmpstr);
+
+- snprintf(tmpstr, sizeof(tmpstr), "fbctrl addr=0x%"PRIx64,
++ snprintf(tmpstr, sizeof(tmpstr), "fbctrl addr=0x%" PRIx64,
+ (uint64_t) DEV_FBCTRL_ADDRESS);
+ device_add(machine, tmpstr);
+
+- snprintf(tmpstr, sizeof(tmpstr), "disk addr=0x%"PRIx64,
++ snprintf(tmpstr, sizeof(tmpstr), "disk addr=0x%" PRIx64,
+ (uint64_t) DEV_DISK_ADDRESS);
+ device_add(machine, tmpstr);
+
+- snprintf(tmpstr, sizeof(tmpstr), "ether addr=0x%"PRIx64" irq=%s."
++ snprintf(tmpstr, sizeof(tmpstr), "ether addr=0x%" PRIx64 " irq=%s."
+ "cpu[%i].3", (uint64_t) DEV_ETHER_ADDRESS, machine->path,
+ machine->bootstrap_cpu);
+ device_add(machine, tmpstr);
+
+- snprintf(tmpstr, sizeof(tmpstr), "rtc addr=0x%"PRIx64" irq=%s."
++ snprintf(tmpstr, sizeof(tmpstr), "rtc addr=0x%" PRIx64 " irq=%s."
+ "cpu[%i].4", (uint64_t) DEV_RTC_ADDRESS, machine->path,
+ machine->bootstrap_cpu);
+ device_add(machine, tmpstr);
+@@ -422,6 +422,3 @@ MACHINE_REGISTER(testsh)
+
+ machine_entry_add_alias(me, "testsh");
+ }
+-
+-
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_main_GXemul.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_main_GXemul.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_main_GXemul.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,20 @@
+$NetBSD: patch-src_main_GXemul.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/main/GXemul.cc.orig 2014-08-17 08:45:14.000000000 +0000
++++ src/main/GXemul.cc
+@@ -515,7 +515,7 @@ string GXemul::Version()
+ #else
+ << "(unknown version)"
+ #endif
+- << " "COPYRIGHT_MSG"\n"SECONDARY_MSG;
++ << " " COPYRIGHT_MSG "\n" SECONDARY_MSG;
+
+ return ss.str();
+ }
+@@ -1164,4 +1164,3 @@ UNITTESTS(GXemul)
+
+
+ #endif
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_old__main_emul.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_old__main_emul.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_old__main_emul.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,53 @@
+$NetBSD: patch-src_old__main_emul.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/old_main/emul.cc.orig 2014-08-17 08:45:12.000000000 +0000
++++ src/old_main/emul.cc
+@@ -118,7 +118,7 @@ static void add_breakpoints(struct machi
+
+ m->breakpoints.addr[i] = dp;
+
+- debug("breakpoint %i: 0x%"PRIx64, i, dp);
++ debug("breakpoint %i: 0x%" PRIx64, i, dp);
+ if (string_flag)
+ debug(" (%s)", m->breakpoints.string[i]);
+ debug("\n");
+@@ -658,26 +658,26 @@ void emul_machine_setup(struct machine *
+
+ case ARCH_MIPS:
+ if (cpu->is_32bit) {
+- debug("0x%08"PRIx32, (uint32_t)
++ debug("0x%08" PRIx32, (uint32_t)
+ m->cpus[m->bootstrap_cpu]->pc);
+ if (cpu->cd.mips.gpr[MIPS_GPR_GP] != 0)
+- debug(" (gp=0x%08"PRIx32")", (uint32_t)
++ debug(" (gp=0x%08" PRIx32 ")", (uint32_t)
+ m->cpus[m->bootstrap_cpu]->cd.mips.gpr[
+ MIPS_GPR_GP]);
+ } else {
+- debug("0x%016"PRIx64, (uint64_t)
++ debug("0x%016" PRIx64, (uint64_t)
+ m->cpus[m->bootstrap_cpu]->pc);
+ if (cpu->cd.mips.gpr[MIPS_GPR_GP] != 0)
+- debug(" (gp=0x%016"PRIx64")", (uint64_t)
++ debug(" (gp=0x%016" PRIx64 ")", (uint64_t)
+ cpu->cd.mips.gpr[MIPS_GPR_GP]);
+ }
+ break;
+
+ default:
+ if (cpu->is_32bit)
+- debug("0x%08"PRIx32, (uint32_t) cpu->pc);
++ debug("0x%08" PRIx32, (uint32_t) cpu->pc);
+ else
+- debug("0x%016"PRIx64, (uint64_t) cpu->pc);
++ debug("0x%016" PRIx64, (uint64_t) cpu->pc);
+ }
+ debug("\n");
+
+@@ -926,4 +926,3 @@ void emul_run(struct emul *emul)
+
+ console_deinit_main();
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_old__main_main.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_old__main_main.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_old__main_main.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,29 @@
+$NetBSD: patch-src_old__main_main.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/old_main/main.cc.orig 2014-08-17 08:45:12.000000000 +0000
++++ src/old_main/main.cc
+@@ -228,7 +228,7 @@ void internal_w(char *arg)
+ static void usage(int longusage)
+ {
+
+- printf("GXemul "VERSION" "COPYRIGHT_MSG"\n"SECONDARY_MSG);
++ printf("GXemul " VERSION " " COPYRIGHT_MSG "\n" SECONDARY_MSG);
+ printf("Read the source code and/or documentation for "
+ "other Copyright messages.\n");
+
+@@ -837,7 +837,7 @@ int main(int argc, char *argv[])
+ }
+
+ /* Print startup message: */
+- debug("GXemul "VERSION" "COPYRIGHT_MSG"\n"SECONDARY_MSG
++ debug("GXemul " VERSION " " COPYRIGHT_MSG "\n" SECONDARY_MSG
+ "Read the source code and/or documentation for other Copyright "
+ "messages.\n\n");
+
+@@ -932,4 +932,3 @@ int main(int argc, char *argv[])
+
+ return 0;
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_old__main_memory.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_old__main_memory.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_old__main_memory.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,42 @@
+$NetBSD: patch-src_old__main_memory.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/old_main/memory.cc.orig 2014-08-17 08:45:12.000000000 +0000
++++ src/old_main/memory.cc
+@@ -378,13 +378,13 @@ void memory_device_register(struct memor
+
+ if (verbose >= 2) {
+ /* (40 bits of physical address is displayed) */
+- debug("device at 0x%010"PRIx64": %s", (uint64_t) baseaddr,
++ debug("device at 0x%010" PRIx64 ": %s", (uint64_t) baseaddr,
+ device_name);
+
+ if (flags & (DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK)
+ && (baseaddr & mem->dev_dyntrans_alignment) != 0) {
+ fatal("\nWARNING: Device dyntrans access, but unaligned"
+- " baseaddr 0x%"PRIx64".\n", (uint64_t) baseaddr);
++ " baseaddr 0x%" PRIx64 ".\n", (uint64_t) baseaddr);
+ }
+
+ if (flags & (DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK)) {
+@@ -627,11 +627,11 @@ void memory_warn_about_unimplemented_add
+ debug("} ");
+ }
+
+- fatal("paddr=0x%"PRIx64" >= physical_max; pc=", paddr);
++ fatal("paddr=0x%" PRIx64 " >= physical_max; pc=", paddr);
+ if (cpu->is_32bit)
+- fatal("0x%08"PRIx32, (uint32_t) old_pc);
++ fatal("0x%08" PRIx32, (uint32_t) old_pc);
+ else
+- fatal("0x%016"PRIx64, (uint64_t) old_pc);
++ fatal("0x%016" PRIx64, (uint64_t) old_pc);
+ symbol = get_symbol_name(&cpu->machine->symbol_context,
+ old_pc, &offset);
+ fatal(" <%s> ]\n", symbol? symbol : " no symbol ");
+@@ -998,4 +998,3 @@ void store_16bit_word_in_host(struct cpu
+ int tmp = data[0]; data[0] = data[1]; data[1] = tmp;
+ }
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_old__main_settings.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_old__main_settings.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_old__main_settings.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,36 @@
+$NetBSD: patch-src_old__main_settings.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/old_main/settings.cc.orig 2014-08-17 08:45:12.000000000 +0000
++++ src/old_main/settings.cc
+@@ -286,19 +286,19 @@ void settings_debugdump(struct settings
+
+ switch (settings->presentation_format[i]) {
+ case SETTINGS_FORMAT_DECIMAL:
+- printf("%"PRIi64, value);
++ printf("%" PRIi64, value);
+ break;
+ case SETTINGS_FORMAT_HEX8:
+- printf("0x%02"PRIx8, (int8_t) value);
++ printf("0x%02" PRIx8, (int8_t) value);
+ break;
+ case SETTINGS_FORMAT_HEX16:
+- printf("0x%04"PRIx16, (int16_t) value);
++ printf("0x%04" PRIx16, (int16_t) value);
+ break;
+ case SETTINGS_FORMAT_HEX32:
+- printf("0x%08"PRIx32, (int32_t) value);
++ printf("0x%08" PRIx32, (int32_t) value);
+ break;
+ case SETTINGS_FORMAT_HEX64:
+- printf("0x%016"PRIx64, (int64_t) value);
++ printf("0x%016" PRIx64, (int64_t) value);
+ break;
+ case SETTINGS_FORMAT_BOOL:
+ printf(value? "true" : "false");
+@@ -503,4 +503,3 @@ int settings_access(struct settings *set
+
+ return SETTINGS_NAME_NOT_FOUND;
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_promemul_arcbios.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_promemul_arcbios.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_promemul_arcbios.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,209 @@
+$NetBSD: patch-src_promemul_arcbios.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/promemul/arcbios.cc.orig 2014-08-17 08:45:15.000000000 +0000
++++ src/promemul/arcbios.cc
+@@ -696,7 +696,7 @@ static uint64_t arcbios_addchild64(struc
+ uint64_t eparent, echild, epeer, tmp;
+ unsigned char buf[8];
+
+- /* debug("[ addchild: peeraddr = 0x%016"PRIx64" ]\n",
++ /* debug("[ addchild: peeraddr = 0x%016" PRIx64 " ]\n",
+ (uint64_t) peeraddr); */
+
+ cpu->memory_rw(cpu, cpu->mem,
+@@ -741,7 +741,7 @@ static uint64_t arcbios_addchild64(struc
+ + ((uint64_t)buf[4] << 32) + ((uint64_t)buf[5] << 40)
+ + ((uint64_t)buf[6] << 48) + ((uint64_t)buf[7] << 56);
+
+- /* debug(" epeer=%"PRIx64" echild=%"PRIx64" eparent=%"PRIx64
++ /* debug(" epeer=%" PRIx64 " echild=%" PRIx64 " eparent=%" PRIx64
+ "\n", (uint64_t) epeer, (uint64_t) echild,
+ (uint64_t) eparent); */
+
+@@ -749,16 +749,16 @@ static uint64_t arcbios_addchild64(struc
+ epeer = a;
+ store_64bit_word(cpu, peeraddr + 0 *
+ machine->md.arc->wordlen, epeer);
+- /* debug("[ addchild: adding 0x%016"PRIx64" as peer "
+- "to 0x%016"PRIx64" ]\n", (uint64_t) a,
++ /* debug("[ addchild: adding 0x%016" PRIx64 " as peer "
++ "to 0x%016" PRIx64 " ]\n", (uint64_t) a,
+ (uint64_t) peeraddr); */
+ }
+ if (peeraddr == parent && echild == 0) {
+ echild = a;
+ store_64bit_word(cpu, peeraddr + 1 *
+ machine->md.arc->wordlen, echild);
+- /* debug("[ addchild: adding 0x%016"PRIx64" as child "
+- "to 0x%016"PRIx64" ]\n", (uint64_t) a,
++ /* debug("[ addchild: adding 0x%016" PRIx64 " as child "
++ "to 0x%016" PRIx64 " ]\n", (uint64_t) a,
+ (uint64_t) peeraddr); */
+ }
+
+@@ -866,8 +866,8 @@ uint64_t arcbios_addchild_manual(struct
+ machine->md.arc->next_component_address +
+ (cpu->machine->md.arc->arc_64bit? 0x18 : 0x0c);
+
+- /* printf("& ADDING %i: configdata=0x%016"PRIx64" "
+- "component=0x%016"PRIx64"\n",
++ /* printf("& ADDING %i: configdata=0x%016" PRIx64 " "
++ "component=0x%016" PRIx64 "\n",
+ machine->md.arc->n_configuration_data,
+ (uint64_t) machine->md.arc->configuration_data_configdata[
+ machine->md.arc->n_configuration_data],
+@@ -946,14 +946,14 @@ static void arcbios_get_msdos_partition_
+ ugly_goto:
+ *start = 0; *size = 0;
+
+- /* printf("reading MSDOS partition from offset 0x%"PRIx64"\n",
++ /* printf("reading MSDOS partition from offset 0x%" PRIx64 "\n",
+ (uint64_t) offset); */
+
+ res = diskimage_access(machine, disk_id, disk_type, 0, offset,
+ sector, sizeof(sector));
+ if (!res) {
+ fatal("[ arcbios_get_msdos_partition_size(): couldn't "
+- "read the disk image, id %i, offset 0x%"PRIx64" ]\n",
++ "read the disk image, id %i, offset 0x%" PRIx64 " ]\n",
+ disk_id, (uint64_t) offset);
+ return;
+ }
+@@ -1236,7 +1236,7 @@ int arcbios_emul(struct cpu *cpu)
+ cpu->cd.mips.gpr[MIPS_GPR_V0] = (int64_t)
+ (int32_t) cpu->cd.mips.gpr[MIPS_GPR_V0];
+ }
+- debug("[ ARCBIOS GetPeer(node 0x%016"PRIx64"): 0x%016"PRIx64
++ debug("[ ARCBIOS GetPeer(node 0x%016" PRIx64 "): 0x%016" PRIx64
+ " ]\n", (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A0],
+ (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_V0]);
+ break;
+@@ -1287,8 +1287,8 @@ int arcbios_emul(struct cpu *cpu)
+ cpu->cd.mips.gpr[MIPS_GPR_V0] = (int64_t)
+ (int32_t)cpu->cd.mips.gpr[MIPS_GPR_V0];
+ }
+- debug("[ ARCBIOS GetChild(node 0x%016"PRIx64"): 0x%016"
+- PRIx64" ]\n", (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A0],
++ debug("[ ARCBIOS GetChild(node 0x%016" PRIx64 "): 0x%016"
++ PRIx64 " ]\n", (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A0],
+ (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_V0]);
+ break;
+ case 0x2c: /* GetParent(node) */
+@@ -1336,19 +1336,19 @@ int arcbios_emul(struct cpu *cpu)
+ cpu->cd.mips.gpr[MIPS_GPR_V0] = (int64_t)
+ (int32_t) cpu->cd.mips.gpr[MIPS_GPR_V0];
+ }
+- debug("[ ARCBIOS GetParent(node 0x%016"PRIx64"): 0x%016"
+- PRIx64" ]\n", (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A0],
++ debug("[ ARCBIOS GetParent(node 0x%016" PRIx64 "): 0x%016"
++ PRIx64 " ]\n", (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A0],
+ (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_V0]);
+ break;
+ case 0x30: /* GetConfigurationData(void *configdata, void *node) */
+- /* fatal("[ ARCBIOS GetConfigurationData(0x%016"PRIx64","
+- "0x%016"PRIx64") ]\n",
++ /* fatal("[ ARCBIOS GetConfigurationData(0x%016" PRIx64 ","
++ "0x%016" PRIx64 ") ]\n",
+ (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A0],
+ (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A1]); */
+ cpu->cd.mips.gpr[MIPS_GPR_V0] = ARCBIOS_EINVAL;
+ for (i=0; i<machine->md.arc->n_configuration_data; i++) {
+ /* fatal("configuration_data_component[%i] = "
+- "0x%016"PRIx64"\n", i, (uint64_t) machine->
++ "0x%016" PRIx64 "\n", i, (uint64_t) machine->
+ md.arc->configuration_data_component[i]); */
+ if (cpu->cd.mips.gpr[MIPS_GPR_A1] ==
+ machine->md.arc->configuration_data_component[i]) {
+@@ -1671,8 +1671,8 @@ int arcbios_emul(struct cpu *cpu)
+ arcbios_handle_to_start_and_size(machine,
+ handleTmp, &partition_offset, &size);
+
+- debug("[ ARCBIOS Write(%i,0x%08"PRIx64",%i,0x%08"
+- PRIx64") ]\n", (int) cpu->cd.mips.gpr[MIPS_GPR_A0],
++ debug("[ ARCBIOS Write(%i,0x%08" PRIx64 ",%i,0x%08"
++ PRIx64 ") ]\n", (int) cpu->cd.mips.gpr[MIPS_GPR_A0],
+ (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A1],
+ (int) cpu->cd.mips.gpr[MIPS_GPR_A2],
+ (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A3]);
+@@ -1718,13 +1718,13 @@ int arcbios_emul(struct cpu *cpu)
+ break;
+ case 0x70: /* Seek(uint32_t handle, int64_t *ofs,
+ uint32_t whence): uint32_t */
+- debug("[ ARCBIOS Seek(%i,0x%08"PRIx64",%i): ",
++ debug("[ ARCBIOS Seek(%i,0x%08" PRIx64 ",%i): ",
+ (int) cpu->cd.mips.gpr[MIPS_GPR_A0],
+ (uint64_t)cpu->cd.mips.gpr[MIPS_GPR_A1],
+ (int) cpu->cd.mips.gpr[MIPS_GPR_A2]);
+
+ if (cpu->cd.mips.gpr[MIPS_GPR_A2] != 0) {
+- fatal("[ ARCBIOS Seek(%i,0x%08"PRIx64",%i): "
++ fatal("[ ARCBIOS Seek(%i,0x%08" PRIx64 ",%i): "
+ "UNIMPLEMENTED whence=%i ]\n",
+ (int) cpu->cd.mips.gpr[MIPS_GPR_A0],
+ (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A1],
+@@ -1752,7 +1752,7 @@ int arcbios_emul(struct cpu *cpu)
+
+ machine->md.arc->current_seek_offset[
+ cpu->cd.mips.gpr[MIPS_GPR_A0]] = ofs;
+- debug("%016"PRIx64" ]\n", (uint64_t) ofs);
++ debug("%016" PRIx64 " ]\n", (uint64_t) ofs);
+ }
+
+ cpu->cd.mips.gpr[MIPS_GPR_V0] = 0; /* Success. */
+@@ -2456,7 +2456,7 @@ void arcbios_init(struct machine *machin
+ machine->md.arc->console_curx = 0;
+ machine->md.arc->console_cury = 0;
+
+- arcbios_putstring(cpu, "GXemul "VERSION" ARCBIOS emulation\n");
++ arcbios_putstring(cpu, "GXemul " VERSION " ARCBIOS emulation\n");
+
+ snprintf(tmpstr, sizeof(tmpstr), "%i cpu%s (%s), %i MB "
+ "memory\n\n", machine->ncpus, machine->ncpus > 1? "s" : "",
+@@ -2609,7 +2609,7 @@ void arcbios_init(struct machine *machin
+
+ system = arcbios_addchild_manual(cpu, COMPONENT_CLASS_SystemClass,
+ COMPONENT_TYPE_ARC, 0,1,2,0, 0xffffffff, name, 0/*ROOT*/, NULL, 0);
+- debug("ARC system @ 0x%"PRIx64" (\"%s\")\n", (uint64_t) system, name);
++ debug("ARC system @ 0x%" PRIx64 " (\"%s\")\n", (uint64_t) system, name);
+
+
+ /*
+@@ -2720,18 +2720,18 @@ void arcbios_init(struct machine *machin
+ 0xffffffff, NULL, cpuaddr, NULL, 0);
+ }
+
+- debug("ARC cpu%i @ 0x%"PRIx64, i, (uint64_t) cpuaddr);
++ debug("ARC cpu%i @ 0x%" PRIx64, i, (uint64_t) cpuaddr);
+
+ if (fpu != 0)
+- debug(" (fpu @ 0x%"PRIx64")\n", (uint64_t) fpu);
++ debug(" (fpu @ 0x%" PRIx64 ")\n", (uint64_t) fpu);
+ else
+ debug("\n");
+
+- debug(" picache @ 0x%"PRIx64", pdcache @ 0x%"PRIx64"\n",
++ debug(" picache @ 0x%" PRIx64 ", pdcache @ 0x%" PRIx64 "\n",
+ (uint64_t) picache, (uint64_t) pdcache);
+
+ if (cpu->cd.mips.cache_secondary >= 12)
+- debug(" sdcache @ 0x%"PRIx64"\n",
++ debug(" sdcache @ 0x%" PRIx64 "\n",
+ (uint64_t) sdcache);
+
+ if (machine->machine_type == MACHINE_SGI) {
+@@ -2740,7 +2740,7 @@ void arcbios_init(struct machine *machin
+ COMPONENT_CLASS_MemoryClass,
+ COMPONENT_TYPE_MemoryUnit, 0, 1, 2, 0,
+ 0xffffffff, "memory", cpuaddr, NULL, 0);
+- debug("ARC memory @ 0x%"PRIx64"\n", (uint64_t) memory);
++ debug("ARC memory @ 0x%" PRIx64 "\n", (uint64_t) memory);
+ }
+ }
+
+@@ -2847,4 +2847,3 @@ void arcbios_init(struct machine *machin
+
+ arc_environment_setup(machine, is64bit, primary_ether_addr);
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_promemul_dec__prom.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_promemul_dec__prom.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_promemul_dec__prom.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,20 @@
+$NetBSD: patch-src_promemul_dec__prom.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/promemul/dec_prom.cc.orig 2014-08-17 08:45:15.000000000 +0000
++++ src/promemul/dec_prom.cc
+@@ -645,7 +645,7 @@ int decstation_prom_emul(struct cpu *cpu
+ cpu->running = 0;
+ break;
+ default:
+- fatal("DEC prom emulation: unknown rex() a0=0x%"PRIx64
++ fatal("DEC prom emulation: unknown rex() a0=0x%" PRIx64
+ " ('%c')\n",
+ (int64_t) cpu->cd.mips.gpr[MIPS_GPR_A0],
+ (char) cpu->cd.mips.gpr[MIPS_GPR_A0]);
+@@ -673,4 +673,3 @@ int decstation_prom_emul(struct cpu *cpu
+
+ return 1;
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_promemul_dreamcast.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_promemul_dreamcast.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_promemul_dreamcast.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,26 @@
+$NetBSD: patch-src_promemul_dreamcast.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+Change vectorAddr to long to handle longer values in switch().
+
+--- src/promemul/dreamcast.cc.orig 2014-08-17 08:45:15.000000000 +0000
++++ src/promemul/dreamcast.cc
+@@ -241,7 +241,7 @@ void dreamcast_emul(struct cpu *cpu)
+ // cpu->pc is the address where PROM emulation was triggered, but
+ // what we are after is the indirect vector that was used to fetch
+ // that address.
+- int vectorAddr = ((cpu->pc & 0x00ffffff) - 0x100 + 0xb0) | 0x8c000000;
++ long vectorAddr = ((cpu->pc & 0x00ffffff) - 0x100 + 0xb0) | 0x8c000000;
+
+ int r1 = cpu->cd.sh.r[1];
+ int r6 = cpu->cd.sh.r[6];
+@@ -382,8 +382,7 @@ bad:
+ cpu_register_dump(cpu->machine, cpu, 1, 0);
+ printf("\n");
+ fatal("[ dreamcast_emul(): unimplemented dreamcast PROM call, "
+- "pc=0x%08"PRIx32" (vectorAddr=0x%08"PRIx32") ]\n", (uint32_t)cpu->pc, vectorAddr);
++ "pc=0x%08" PRIx32 " (vectorAddr=0x%08" PRIx32 ") ]\n", (uint32_t)cpu->pc, vectorAddr);
+ cpu->running = 0;
+ return;
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_promemul_ps2__bios.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_promemul_ps2__bios.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_promemul_ps2__bios.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,46 @@
+$NetBSD: patch-src_promemul_ps2__bios.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/promemul/ps2_bios.cc.orig 2014-08-17 08:45:15.000000000 +0000
++++ src/promemul/ps2_bios.cc
+@@ -59,12 +59,12 @@ int playstation2_sifbios_emul(struct cpu
+ cpu->cd.mips.gpr[MIPS_GPR_V0] = 0x200; /* TODO */
+ break;
+ case 1: /* halt(int mode) */
+- debug("[ SIFBIOS halt(0x%"PRIx64") ]\n",
++ debug("[ SIFBIOS halt(0x%" PRIx64 ") ]\n",
+ (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A1]);
+ cpu->running = 0;
+ break;
+ case 2: /* setdve(int mode) */
+- debug("[ SIFBIOS setdve(0x%"PRIx64") ]\n",
++ debug("[ SIFBIOS setdve(0x%" PRIx64 ") ]\n",
+ (uint64_t) cpu->cd.mips.gpr[MIPS_GPR_A1]);
+ break;
+ case 3: /* putchar(int ch) */
+@@ -108,8 +108,8 @@ int playstation2_sifbios_emul(struct cpu
+ cpu->cd.mips.gpr[MIPS_GPR_V0] = 1; /* TODO */
+ break;
+ case 64:
+- fatal("[ SIFBIOS SBR_IOPH_INIT(0x%"PRIx32",0x%"PRIx32",0x%"
+- PRIx32"): TODO ]\n",
++ fatal("[ SIFBIOS SBR_IOPH_INIT(0x%" PRIx32 ",0x%" PRIx32 ",0x%"
++ PRIx32 "): TODO ]\n",
+ (uint32_t) cpu->cd.mips.gpr[MIPS_GPR_A1],
+ (uint32_t) cpu->cd.mips.gpr[MIPS_GPR_A2],
+ (uint32_t) cpu->cd.mips.gpr[MIPS_GPR_A3]);
+@@ -163,7 +163,7 @@ int playstation2_sifbios_emul(struct cpu
+ cpu->cd.mips.gpr[MIPS_GPR_V0] = 0;
+ break;
+ case 65:
+- fatal("[ SIFBIOS alloc iop heap(0x"PRIx32") ]\n",
++ fatal("[ SIFBIOS alloc iop heap(0x" PRIx32 ") ]\n",
+ (uint32_t)cpu->cd.mips.gpr[MIPS_GPR_A1]);
+
+ /*
+@@ -232,4 +232,3 @@ int playstation2_sifbios_emul(struct cpu
+
+ return 1;
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_symbol_symbol.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_symbol_symbol.cc:1.1
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_symbol_symbol.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,38 @@
+$NetBSD: patch-src_symbol_symbol.cc,v 1.1 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/symbol/symbol.cc.orig 2014-08-17 08:45:15.000000000 +0000
++++ src/symbol/symbol.cc
+@@ -133,7 +133,7 @@ char *get_symbol_name_and_n_args(struct
+ "%s", s->name);
+ else
+ snprintf(symbol_buf, SYMBOLBUF_MAX,
+- "%s+0x%"PRIx64, s->name, (uint64_t)
++ "%s+0x%" PRIx64, s->name, (uint64_t)
+ (addr - s->addr));
+ if (offset != NULL)
+ *offset = addr - s->addr;
+@@ -157,7 +157,7 @@ char *get_symbol_name_and_n_args(struct
+ "%s", s->name);
+ else
+ snprintf(symbol_buf, SYMBOLBUF_MAX,
+- "%s+0x%"PRIx64, s->name, (uint64_t)
++ "%s+0x%" PRIx64, s->name, (uint64_t)
+ (addr - s->addr));
+
+ if (offset != NULL)
+@@ -318,7 +318,7 @@ void symbol_readfile(struct symbol_conte
+ addr = strtoull(b1, NULL, 16);
+ len = strtoull(b2, NULL, 16);
+ type = b3[0];
+- /* printf("addr=%016"PRIx64" len=%016"PRIx64" type=%i\n",
++ /* printf("addr=%016" PRIx64 " len=%016" PRIx64 " type=%i\n",
+ addr, len, type); */
+
+ if (type == 't' || type == 'r' || type == 'g')
+@@ -418,4 +418,3 @@ void symbol_init(struct symbol_context *
+ sc->sorted_array = 0;
+ sc->n_symbols = 0;
+ }
+-
Index: pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__dreamcast__gdrom.cc
diff -u /dev/null pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__dreamcast__gdrom.cc:1.3
--- /dev/null Wed Mar 21 17:39:42 2018
+++ pkgsrc/emulators/gxemul/patches/patch-src_devices_dev__dreamcast__gdrom.cc Wed Mar 21 17:39:42 2018
@@ -0,0 +1,20 @@
+$NetBSD: patch-src_devices_dev__dreamcast__gdrom.cc,v 1.3 2018/03/21 17:39:42 kamil Exp $
+
+Fix C++11 literals.
+
+--- src/devices/dev_dreamcast_gdrom.cc.orig 2014-08-17 08:45:12.000000000 +0000
++++ src/devices/dev_dreamcast_gdrom.cc
+@@ -474,7 +474,7 @@ DEVICE_ACCESS(dreamcast_gdrom_dma)
+ // GDROM DMA transfer.
+ uint32_t dst = d->dma_reg[0x04 / sizeof(uint32_t)];
+ int length = d->dma_reg[0x08 / sizeof(uint32_t)];
+- fatal("[ dreamcast_gdrom_dma: Transfering %i bytes to 0x%08"PRIx32" ]\n", length, dst);
++ fatal("[ dreamcast_gdrom_dma: Transfering %i bytes to 0x%08" PRIx32 " ]\n", length, dst);
+
+ if (d->data == NULL) {
+ fatal("dreamcast_gdrom_dma: DMA transfer but d->data is NULL. TODO\n");
+@@ -537,4 +537,3 @@ DEVINIT(dreamcast_gdrom)
+
+ return 1;
+ }
+-
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