CVS commit: pkgsrc/cad/verilog-current

["Joerg Sonnenberger" <joerg%netbsd.org@localhost>]

Module Name:    pkgsrc
Committed By:   joerg
Date:           Thu May 23 15:00:00 UTC 2013

Modified Files:
        pkgsrc/cad/verilog-current: distinfo
Added Files:
        pkgsrc/cad/verilog-current/patches: patch-net__scope.cc

Log Message:
Casting 0 to an iterator is not portable. Just use end() in that case.


To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 pkgsrc/cad/verilog-current/distinfo
cvs rdiff -u -r0 -r1.1 pkgsrc/cad/verilog-current/patches/patch-net__scope.cc

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.