CVS commit: pkgsrc/cad/verilog

["Matthias Drochner" <drochner%netbsd.org@localhost>]

Module Name:    pkgsrc
Committed By:   drochner
Date:           Wed Apr 13 14:19:29 UTC 2011

Modified Files:
        pkgsrc/cad/verilog: Makefile PLIST distinfo
        pkgsrc/cad/verilog/patches: patch-aa patch-ad
Removed Files:
        pkgsrc/cad/verilog/patches: patch-ab

Log Message:
update to 0.9.4
changes:
-Language Coverage:
 -Add support for using the &&, || and ! operators with real
  constant values
 -Add support for passing -0.0 from the compiler to the run time
 -Add support for parsing pull devices that have two strengths specified
 -Allow multiple attribute instances
-bugfixes
pkgsrc change: clean up DESTDIR support


To generate a diff of this commit:
cvs rdiff -u -r1.33 -r1.34 pkgsrc/cad/verilog/Makefile
cvs rdiff -u -r1.8 -r1.9 pkgsrc/cad/verilog/PLIST
cvs rdiff -u -r1.15 -r1.16 pkgsrc/cad/verilog/distinfo
cvs rdiff -u -r1.11 -r1.12 pkgsrc/cad/verilog/patches/patch-aa
cvs rdiff -u -r1.9 -r0 pkgsrc/cad/verilog/patches/patch-ab
cvs rdiff -u -r1.9 -r1.10 pkgsrc/cad/verilog/patches/patch-ad

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.