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CVS commit: pkgsrc/cad/verilog

Module Name:    pkgsrc
Committed By:   dmcmahill
Date:           Wed Mar 11 02:08:08 UTC 2009

Modified Files:
        pkgsrc/cad/verilog: Makefile PLIST distinfo

Log Message:
update to verilog-0.8.7, the latest in the stable 0.8 series.

Release Notes for Icarus Verilog 0.8.7

none (but see below for other releases since the last version in pkgsrc)

Release Notes for Icarus Verilog 0.8.6

This is a bug fix update of the 0.8 stable version of Icarus
Verilog. The v0.8 series tries to remain as stable as possible while
still fixing bugs that are safe to fix.


* Fix parse/preprocess of C-style comments in surpressed ifdef

* Support leading underscore in preprocessor names.

Compilation/elaboration issues:

* Support min:typ:max expressions in more places.

* Fix handling of @* non-input nets.

* Do not support system functions in continuous assignments.
* Do not support converting vectors to real.
* Do not support constant real valued expressions.

Run-time ussues:

* Fix comparison of negative numbers that happen to be equal.

* Fix bad execution of certain expressions caused by code generator
  bad lookaside handling.

* Proper error message for invalid bit selects.

* Implement $printtimescale system task.

Compiler build issues:

* Compile OK evel if libbzip2 is not installed, but do not support
  LXT2 in that case.

Release Notes for Icarus Verilog 0.8.5

This is mostly a bug-fix release for the 0.8 stable branch.

* Fix assertions from unary operators with certain operand widths.

* Fix incorrect comparison results when in certain cases comparing two
signed negative integers.

* Latch synthesis has been added to the core synthesizer

* Add nand gate support to the edif code generator

* Minor compile time errors/warnings
* Improved messages from the configure script

Release Notes for Icarus Verilog 0.8.4

This is a bug-fix release for the 0.8 stable branch. The 0.8 stable
branch updates do not include significant new features (they go into
the devel branch instead) nor fixes that are deemed to drastic to
include in a stable tool.

- Various source code portability problems have been fixed. The 0.8 no
  longer compiles on many modern systems.

- Various bug reports have been put to rest with this release. Some
  parser errors have been fixed (including a few regressions from
  0.8.3) and a few new syntaxes added.

- A variety of systhesis bug fixes and enhancements are included in
  0.8.4. Currently, synthesis is only actively supported in the 0.8
  branch, and the 0.8.4 is the most complete.

To generate a diff of this commit:
cvs rdiff -u -r1.30 -r1.31 pkgsrc/cad/verilog/Makefile
cvs rdiff -u -r1.6 -r1.7 pkgsrc/cad/verilog/PLIST
cvs rdiff -u -r1.12 -r1.13 pkgsrc/cad/verilog/distinfo

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

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