Subject: CVS commit: pkgsrc/cad/verilog
To: None <pkgsrc-changes@NetBSD.org>
From: Dan McMahill <email@example.com>
Date: 10/04/2006 23:52:48
Module Name: pkgsrc
Committed By: dmcmahill
Date: Wed Oct 4 23:52:48 UTC 2006
pkgsrc/cad/verilog: Makefile distinfo
update to verilog-0.8.3
** Release Notes for Icarus Verilog 0.8.3
This is a new release of the stable 0.8 branch. The changes from 0.8.2
are intended to be evolutionary, rather then revolutionary, to enhance
the stability of the branch.
Various simulator bugs have been fixed, including (but not limited to):
- Detect overrun of timescale vs. precision
- Handle more operators in constant expressions
- Various ivl crashes and panics fixed.
- Some performance bottlenecks have been fixed.
- Various tool compilation problems have been fixed.
Also, the internal synthesizer (for synthesis targets) has been
considerably improved. NOTE that the code generators have not been
improved to take advantage of all the changes here, so there is work
yet to be done.
The mingw build process for compiling in Windows has been reworked. It
is now possible (indeed preferable) to compile fully native Icarus
Verilog binaries on Windows with no Cygwin tools at all.
To generate a diff of this commit:
cvs rdiff -r1.29 -r1.30 pkgsrc/cad/verilog/Makefile
cvs rdiff -r1.10 -r1.11 pkgsrc/cad/verilog/distinfo
cvs rdiff -r1.7 -r1.8 pkgsrc/cad/verilog/patches/patch-ad
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.