Subject: CVS commit: pkgsrc/cad/verilog-current
To: None <>
From: Dan McMahill <>
List: pkgsrc-changes
Date: 08/11/2006 13:28:08
Module Name:	pkgsrc
Committed By:	dmcmahill
Date:		Fri Aug 11 13:28:08 UTC 2006

Modified Files:
	pkgsrc/cad/verilog-current: Makefile PLIST distinfo
	pkgsrc/cad/verilog-current/patches: patch-ad

Log Message:
Update to 20060809 snapshot.  There have been several changes since the
last packaged snapshot.  Those are:

Release Notes for Icarus Verilog Snapshot 20060215

* Part select of memory words should now work according to
  Verilog-2001. This also led to some cleanup of the handling of types
  internally, as well as some infrastructure for general arrays.

* Minor fix to parsing of (* *) attributes.

* Fix rounding of reals to integers.

* Clean up some of the vvp engine related to memories. Remove some
  dead instructions.

Release Notes for Icarus Verilog Snapshot 20060409

the most substantial difference in this snapshot the first signs of
generate support. The compiler now supports generate loops and has
been tested with examples that include wires and gates within the
generate scheme. The regression test suite has very few generate
tests, so any concise self-testing test programs that use generate
would be helpful.

Also, instance arrays that use overridden parameters now work

Task arguments are a bit more flexible in order to support vendor
(notably Xilinx) models that use more interesting task arguments.

Runtime support for bi-directional ports had some bugs fixed, along
with some other minor run-time bugs. Also, the runtime gains support
for typed parameters. And also, there are some new runtime callbacks
for events and memories.

Parameters had a few types related bugs fixed. They are a bit more
flexible now.

And various minor compilation errors have been fixed. This includes
C/C++ compilation errors fixes, and some configure/Makefile tweaks.

Release Notes for Icarus Verilog Snapshot 20060618

Add support for system functions in continuous assignments.

Allow concatenations as arguments to inout ports. This comes with a
small variety of internal part select and concatenation bug fixes.

Fix some bugs in constant propagation through ternary expressions.
Fix broken subtraction if small constants in certain cases.
Fix a few datatype mismatch errors.

Make $readmem give warning when input is inadequate for requested

Fix runtime of nand in continuous assignments.

Fix synchronous user defined primiteves to only follow edges.

Fix a runtime error in some thread delays processing.

Improve limited genvar expression handling.

Start a rework of expression elaboration. Make elaboration aware of
the expression context width when appropriate in order to better
handle expression width and padding.

Fix the make rules for to reflect that they come from the
same source. Fix the to configure the stub target.

Fix portability of the lexor source files on Windows systems. Get rid
of the isatty references.

Make a stub lround when the system version is missing.

* Release Notes for Snapshot 20060809

Some handling of real values is improved. Real valued literals are
handled in net contexts (continuous assignment, etc.). Also, modulus
of real operands now works. (This is an extension to the Verilog

The power operator (**) now works.

Signed right shift works properly now.

The $sscanf and $fscanf are introduced, and work at least for basic
numeric values.

The release function now works to undo general force statements, and
not just contant force statements.

Delay constants up to 64 bits are supported. This at first doesn't
seem like an issue, but when precisions are mixed, it becomes
surprisingly easy to overflow 32bit delays.

The driver is reworked to pass many preprocessor details through a
temporary file instead of on the command line of a system(3)
call. This prevents confusing and incorrect shell processing of
complex strings passed as values to -D flags.

Various other little fixes.

To generate a diff of this commit:
cvs rdiff -r1.51 -r1.52 pkgsrc/cad/verilog-current/Makefile
cvs rdiff -r1.8 -r1.9 pkgsrc/cad/verilog-current/PLIST
cvs rdiff -r1.7 -r1.8 pkgsrc/cad/verilog-current/
cvs rdiff -r1.25 -r1.26 pkgsrc/cad/verilog-current/distinfo
cvs rdiff -r1.12 -r1.13 pkgsrc/cad/verilog-current/patches/patch-ad

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.