Module Name:	pkgsrc
Committed By:	dmcmahill
Date:		Sat May  6 19:13:55 UTC 2006

Modified Files:
	pkgsrc/cad/verilog: Makefile PLIST distinfo

Log Message:
update to verilog-0.8.2.  Adds edif output, contains several bug fixes for
compatibility with more c++ compilers.


To generate a diff of this commit:
cvs rdiff -r1.25 -r1.26 pkgsrc/cad/verilog/Makefile
cvs rdiff -r1.4 -r1.5 pkgsrc/cad/verilog/PLIST
cvs rdiff -r1.9 -r1.10 pkgsrc/cad/verilog/distinfo

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.