Subject: CVS commit: pkgsrc/cad/verilog-current
To: None <pkgsrc-changes@NetBSD.org>
From: Dan McMahill <dmcmahill@netbsd.org>
List: pkgsrc-changes
Date: 11/27/2004 02:50:09
Module Name:	pkgsrc
Committed By:	dmcmahill
Date:		Sat Nov 27 02:50:09 UTC 2004

Modified Files:
	pkgsrc/cad/verilog-current: Makefile distinfo

Log Message:
update to verilog-current 20041004.

Release Notes for Icarus Verilog Snapshot 20041004

Some minor Makefile bugs have been fixed, and source file text
formatting has in some cases been normalized for release. Also,
configure scripts have been factored for a more consistent build.

Fixed continuous assignments to carry strength when needed for correct
behavior. This bug led to subtly incorrect reset behavior, but could
have caused strength modeling errors in a variety of situations.

Fixed some <= vs >= behaviors to be consistent. The results of these
comparisons, when sized values are involved, are more standard now.


To generate a diff of this commit:
cvs rdiff -r1.43 -r1.44 pkgsrc/cad/verilog-current/Makefile
cvs rdiff -r1.22 -r1.23 pkgsrc/cad/verilog-current/distinfo

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.