Subject: CVS commit: pkgsrc/cad/verilog-current
To: None <>
From: Dan McMahill <>
List: pkgsrc-changes
Date: 09/21/2004 02:23:19
Module Name:	pkgsrc
Committed By:	dmcmahill
Date:		Tue Sep 21 02:23:19 UTC 2004

Modified Files:
	pkgsrc/cad/verilog-current: Makefile distinfo

Log Message:
update to verilog-current-20040915.  Changes in this snapshot:

The big news is that module instance arrays now work. Gate and UDP
instance arrays have worked for a while, but module instance arrays
were more tricky because of the scope arrys they create. The issues
have been dealt with, and module instance arrays are now supported.

An interesting but subtle set of bugs in the evaluation of ternary
expressions has been fixed. The problems expressed themselves when the
condition expression was constant.

Degenerate wait statements now work properly.

The @* syntax apparently missed sensitivities in l-value expressions
of assignment statements. This led to subtle bugs in carefully crafted
bits of code.

Verilog attributes are properly parsed in a few more contexts. Also,
some specify syntax cases have been fixed.

Some minor spelling and documentation errors have been fixed, along
with assorted compiler warnings.

To generate a diff of this commit:
cvs rdiff -r1.41 -r1.42 pkgsrc/cad/verilog-current/Makefile
cvs rdiff -r1.21 -r1.22 pkgsrc/cad/verilog-current/distinfo

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.