Subject: CVS commit: pkgsrc/cad/verilog-current
To: None <>
From: Dan McMahill <>
List: pkgsrc-changes
Date: 06/07/2004 01:09:50
Module Name:	pkgsrc
Committed By:	dmcmahill
Date:		Mon Jun  7 01:09:50 UTC 2004

Modified Files:
	pkgsrc/cad/verilog-current: Makefile distinfo

Log Message:
update to verilog-current-20040606

* Release Notes for Icarus Verilog Snapshot 20040606

Ports of primitives can bind by name as well as by position. Also
support Verilog 2001 style port declarations for primitives.

System function return types can now be specified by system function
table files. System Function Table Files are described in the iverilog
man page. Also include better system function return types in VPI.

Non-blocking assign of real values to real variables now works.

Properly handle nul strings ("") as 8bit values. This is a weirdness
legacy of XL.

Fix some synthesis problems for logical OR and logical AND. Bitwise OR
and AND were fine. These fixes affected simulation as well.

Handle wait statements with all sorts of constant values. These are
sometimes weird, bug legal.

Handle Negative value reals, and a few other bugs related to real

Change internal use of identifiers to perm_strings for better

Functions returning unsupported types now generate error
messages. Previously, they would quietly generate bad
code. Infrastructure is also added to eventually support arbitrary
function return types.

Better compile-time support for Cygwin vs mingw32.

The ipal target is removed from this source. (ipal is now an add-on
package that is compiled seperately.)

To generate a diff of this commit:
cvs rdiff -r1.39 -r1.40 pkgsrc/cad/verilog-current/Makefile
cvs rdiff -r1.19 -r1.20 pkgsrc/cad/verilog-current/distinfo

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.