Subject: CVS commit: pkgsrc/cad/covered
To: None <>
From: Dan McMahill <>
List: pkgsrc-changes
Date: 08/24/2003 18:38:08
Module Name:	pkgsrc
Committed By:	dmcmahill
Date:		Sun Aug 24 18:38:08 UTC 2003

Update of /cvsroot/pkgsrc/cad/covered
In directory

Log Message:
import covered-0.2.1

Covered is a Verilog code coverage analysis tool that can be useful
for determining how well a diagnostic test suite is covering the
design under test. Typically in the design verification work flow, a
design verification engineer will develop a self-checking test suite
to verify design elements/functions specified by a design's
specification document. When the test suite contains all of the tests
required by the design specification, the test writer may be asking
him/herself, "How much logic in the design is actually being
exercised?", "Does my test suite cover all of the logic under test?",
and "Am I done writing tests for the logic?".  When the design
verification gets to this point, it is often useful to get some
metrics for determining logic coverage. This is where a code coverage
utility, such as Covered, is very useful.

Please note that this package is for a stable release version.
There is a seperate package (covered-current) which is made of
development snapshots.

Vendor Tag:	TNF
Release Tags:	pkgsrc-base
N pkgsrc/cad/covered/Makefile
N pkgsrc/cad/covered/DESCR
N pkgsrc/cad/covered/distinfo
N pkgsrc/cad/covered/PLIST
N pkgsrc/cad/covered/patches/patch-aa

No conflicts created by this import