Subject: CVS commit: pkgsrc/cad/verilog-current
To: None <pkgsrc-changes@netbsd.org>
From: Dan McMahill <dmcmahill@netbsd.org>
List: pkgsrc-changes
Date: 10/22/2002 05:52:19
Module Name:	pkgsrc
Committed By:	dmcmahill
Date:		Tue Oct 22 02:52:19 UTC 2002

Modified Files:
	pkgsrc/cad/verilog-current: Makefile distinfo
Removed Files:
	pkgsrc/cad/verilog-current/patches: patch-aa

Log Message:
update to verilog-current-20021019

Release Notes for Icarus Verilog Snapshot 20021019

The synthesizer now detects asynchronous set/reset inputs to DFF
devices. The fpga and vvp code generators have been updated to support
these signals.

The vvp code generator also gained some register management code that
improves the thread register usage. This redoces code size for certain
common cases, and thus improves simulation performance.

The requirements on `ifdef and related compiler directives has been
relaxed, to correspond to more common behavior.

The parameter range support crashed if the range expressions had
parameters in them. This is fixed, and some signed-ness bugs fixed
along with it.

Rearrange some of the configure script tests to assure better
compatibility accross platforms.


To generate a diff of this commit:
cvs rdiff -r1.30 -r1.31 pkgsrc/cad/verilog-current/Makefile
cvs rdiff -r1.14 -r1.15 pkgsrc/cad/verilog-current/distinfo
cvs rdiff -r1.10 -r0 pkgsrc/cad/verilog-current/patches/patch-aa

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.