Subject: CVS commit: pkgsrc/cad/verilog-current
To: None <email@example.com>
From: Dan McMahill <firstname.lastname@example.org>
Date: 08/29/2002 14:15:58
Module Name: pkgsrc
Committed By: dmcmahill
Date: Thu Aug 29 11:15:57 UTC 2002
pkgsrc/cad/verilog-current: Makefile distinfo
update to verilog-current-20020828
Release Notes for Snapshot 20020828
This snapshot adds support for parameter and localparam bit
ranges. This is a IEEE1364-2001 feature, although some -1995 compilers
have supported it in the past.
Fixed a *nasty* and slippery bug with the evaluation of bit select of
nets. (Bit select of variables was unaffected.) The symptoms did not
clearly point to the problem, so bugs related to it were often mis-
Gate delays were lost when constants were propagated to their
inputs. This is fixed for the known broken cases. Also, mux output
delays have been fixed. Also, release statements that apply to elided
nets are turned into no-ops.
The r-values of non-blocking assignments are now precalculated at
compile time, if possible, as is done with blocking assignments. This
speeds up constant propagation, and is more thorough.
Also optimize subtraction of small constants from vectors, with the
new %subi instruction in vvp. This saves some in code size and thread
Handling of x in r-value bit selects and memory word selects did the
wrong thing. Now they do the right thing. Also, x in the selector of
?: ternary operators does the right (and complicated) thing now. In
the process, a fork-join code generator bug was fixed.
Several bugs with time formatting have been fixed.
Temporaries in sequential blocks are detected by the synthesizer, and
converted into wires when needed. This expands support for
combinational logic synthesis.
To generate a diff of this commit:
cvs rdiff -r1.27 -r1.28 pkgsrc/cad/verilog-current/Makefile
cvs rdiff -r1.11 -r1.12 pkgsrc/cad/verilog-current/distinfo
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.